This paper presents a design of digital control based on a fixed-point model for an application of a single phase AC-DC boost Converter with a high power factor and low current distortion. The system uses a simple closed-loop control with a slow voltage loop (outer loop) to stabilize the output DC bus voltage at the required level and a fast current loop (inner loop) to achieve input power factor correction. The digital control uses a fixed-point structure that improves the control accuracy without increasing the number of arithmetic operations and does not require specific running conditions. The behavior of the system is fully verified by using a digital simulation under Matlab/Simulink environment and experimentally with an implementation in real-time using Xilinx ISE 14.7 software, hardware description language VHDL, Xilinx FPGA ML605 board, and EVAL-AD7656 evaluation board for high-speed analog-to-digital conversion. The obtained results show a good agreement between experiments and simulations for steady-state and transient-responses.

In this paper, a three-phase shunt active power filter (SAPF) controller with a fully digital implementation is presented. The main goal of this contribution is to implement a digital direct power control (DDPC) algorithm without phase-locked-loop (PLL) for SAPF. This algorithm is intended for power quality improvement and current harmonic elimination. The controller introduced in this paper is cost-effective, has a fast-dynamic response, and has a simple hardware implementation. In order to comply with the above specifications, a dedicated controller has been conceived and fully implemented within a field-programmable gate array (FPGA) device. This FPGA-based controller integrates the whole signal-processing functions needed to drive the SAPF, as well as an original method for sector identification. The intended controller provides the desired power references to select the optimal switching sequences. The switching orders follow the grid reference to drive the voltage source inverter (VSI), so the SAPF achieves good performances while ensuring balanced overall supply currents, unity power factor, and reduced harmonic load currents. The proposed digital implementation achieves a valuable compromise between fast dynamic response, minimum execution time, and reduced FPGA resources, through a simple hardware design implementation. The entire system is developed and simulated using VHDL and VHDL-AMS languages.

Partial shading conditions (PSCs) in photovoltaic (PV) systems generate multiple local maximum power points (LMPPs) and a single global maximum power point (GMPP) in the power–voltage (P–V) characteristics, challenging conventional maximum power point tracking (MPPT) methods. This study presents an FPGA-in-the-Loop (FIL) co-simulation of a Systematic-Sequencing Adaptive Particle Swarm Optimization (SS-APSO) algorithm for MPPT under dynamically varying shading conditions. The proposed method combines deterministic particle initialization, adaptive particle reordering, and switching among wide exploration, re-exploration and exploitation modes to enhance global search capability. The controller is implemented on a Xilinx Artix-7 FPGA using fixed-point arithmetic and a finite-state-machine architecture in VHDL and is evaluated through MATLAB/Simulink–FIL co-simulation for two PV configurations: four series-connected modules (4S) and two parallel-connected strings of two series modules (2S2P). The results demonstrate tracking efficiencies generally exceeding 98% under different shading within 0.181 s for both configurations, while in FIL co-simulation, it reaches the GMPP within 0.203. The close agreement between simulation and FIL co-simulation results demonstrates the effectiveness of the proposed SS-APSO-MPPT controller for PV systems.