A complementary noise-canceling CMOS low-noise amplifier (LNA) with enhanced linearity is proposed. An active shunt feedback input stage offers input matching, while extended input matching bandwidth is acquired by a π-type matching network. The intrinsic noise cancellation mechanism maintains acceptable noise figure (NF) with reduced power consumption due to the current reuse principle. Multiple complementary nMOS and pMOS configurations commonly restrain nonlinear components in individual stage of the LNA. Complementary multigated transistor architecture is further employed to nullify the third-order distortion of noise-canceling stage and compensate the second-order nonlinearity of that. High third-order input intercept point (IIP3) is thus obtained, while the second-order input intercept point (IIP2) is guaranteed by differential operation. Implemented in a 0.18-μm CMOS process, the experimental results show that the proposed LNA provides a maximum gain of 17.5 dB and an input 1-dB compression point (IP1 dB) of -3 dBm. An NF of 2.9-3.5 dB and an IIP3 of 10.6-14.3 dBm are obtained from 0.1 to 2 GHz, respectively. The circuit core only draws 9.7 mA from a 2.2 V supply.

A wideband differential linear low-noise transconductance amplifier (LNTA) is proposed for SAW-less applications. An active combiner provides a dual-loop feedback for wideband matching with power efficiency. Operating as an auxiliary common source (CS) stage, complementary multi-gated transistor (MGTR) configurations are employed to compensate for the second- and third-order nonlinearity of the main CS stage, improving small-signal linearity. Large-signal linearity is also enhanced due to Class AB configurations. Additionally, the push-pull operation of the main CS stage and the auxiliary CS stage preserves good large-signal input matching performance. Implemented in a 0.18-μm CMOS process, the measured LNTA chip provides a minimum noise figure (NF) of 2.5 dB, and a maximum transconductance value of 76.7 mS from 0.1 to 3.1 GHz. On average, an input 1-dB compression point (IP1 dB) of 2.3 dBm and an input third-order intercept point (IIP3) of 17.8 dBm are obtained, respectively. The blocker NF is 4.0 dB under a 0 dBm blocker injection while the S₁₁ < -10 dB is maintained even with the blocker input of -3.1 dBm. The LNTA core only draws 13.3 mA from a 1.8 V supply.

Simple authentication protocols based on conventional physical unclonable functions (PUFs) are vulnerable to modeling attacks and other security threats. This article proposes an arbiter PUF based on a linear feedback shift register (LFSR-APUF). Different from the previously reported linear feedback shift register (LFSR) for challenge extension, the proposed scheme feeds the external random challenges into the LFSR module to obfuscate the linear mapping relationship between the challenge and response. It can prevent attackers from obtaining valid challenge–response pairs (CRPs), increasing its resistance to modeling attacks significantly. A 64-stage LFSR-APUF has been implemented on a field programmable gate array (FPGA) board. The experimental results reveal that the proposed design can effectively resist various modeling attacks, such as logistic regression (LR), evolutionary strategy (ES), artificial neuro network (ANN), and support vector machine (SVM) with a prediction rate of 51.79% and a slight effect on the randomness, reliability, and uniqueness. Further, a lightweight authentication protocol is established based on the proposed LFSR-APUF. The protocol incorporates a low-overhead, ultralightweight, novel private bit conversion Cover function that is uniquely bound to each device in the authentication network. The proposed authentication protocol not only resists spoofing attacks, physical attacks, and modeling attacks effectively but also ensures the security of the entire authentication network by transferring important information in encrypted form from the server to the database even when the attacker completely controls the server.

Flicker noise contributed by active mixers usually compromises the overall sensitivity level of direct-conversion receivers (DCRs). In this article, a qualitative quasi-analytical model has been developed to in-depth explain the flicker noise mechanism existing in the switched-g _m active mixer in which an improved current source switch is presented for high mixer common-mode rejection ratio (MCMRR). The built model simply explains how frequency translations take place within the mixer. Compact equations are derived to estimate the flicker noise contribution of individual stages at the output. Simulations validate the accuracy of the predictions, and the dependence of flicker noise on local oscillator (LO) slope ratio, period, and other circuit parameters. The high-frequency limitation of the mixer is further estimated by investigating into the tail parasitic capacitance charging and discharging behavior. Furthermore, a switched-g _m pMOS mixer prototype with low flicker noise is implemented in a 0.18- $\mu \text{m}$ CMOS process. It operates at an RF input frequency of 1 GHz and provides a maximal conversion gain of 12.9 dB and an NF of 11.4 dB while a flicker noise corner of 220 kHz and an IIP3 of 3.6 dBm are measured, respectively. The mixer core only consumes 3.3 mW from a 1.8 V supply.