The automated optical inspection (AOI) has replaced the manual optical inspection of printed circuit boards (PCBs) in nearly all manufacturing lines. Programming the inspection machines is time consuming and requires a good understanding of the optical inspection domain and printed circuit boards. The process of creating such inspection programs needs to be simplified to enable the user to get to inspection results easier and faster. Over the last few years better and affordable computational hardware helped developing the field of artificial neural networks, called deep learning, to an extent, that it surpassed other state of the art approaches and is used in many optical classification tasks since then. With the ongoing trend of Industry 4.0 AOI systems started not only producing but also storing vast amounts of data. This has the potential to aid the improvement of the inspection machines. This paper will discuss key aspects of AOI as well as basics of deep learning and proposes a new way to integrate these techniques for the manufacturers and users of AOI machines. Additionally, the process of programming AOI inspections will be faster.

System families are a form of high level reuse of de- velopment assets in a specific problem domain, by mak- ing use of commonalities and variabilities. To represent assets belonging to the core of the family and assets be- longing to variable parts, feature modeling is a widely used concept. Consistency checking in feature models is not yet addressed appropriately by current methods. This paper gives a brief overview of feature modeling and elaborates the problems of current approaches. Based on the applications of these approaches within an ongoing research project this paper proposes a formalized defini- tion for feature modeling using the Object Constraint Language (OCL) and a set of associations and con- straints to be used in the feature model. The relations be- tween features in the feature model and features to exter- nal assets are examined and a way to formally handle these relations is presented as a result of a research proj- ect.

Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. When using the full potential of FPGAs, it is possible to dynamically reconfigure parts of them during run time without the need to stop the device. This feature is called dynamic partial reconfiguration (DPR). If the DPR approach is to be applied in a real-time application-specific soft-core processor, an architecture must be created that ensures strict compliance with the real-time constraint at all times. In this paper, a novel method that addresses this problem is introduced, and its realization is described. In the first step, an application-specializable soft-core processor is presented that is capable of solving problems while adhering to hard real-time deadlines. This is achieved by the full design time analyzability of the soft-core processor. Its special architecture and other necessary features are discussed. Furthermore, a method for the optimized generation of partial bitstreams for the DPR as well as its practical implementation in a tool is presented. This tool is able to minimize given bitstreams with the help of a differential frame bitmap. Experiments that realize the DPR within the soft-core framework are presented, with respect to the need for hard real-time capability. Those experiments show a significant resource reduction of about 40% compared to a functionally equivalent non-DPR design.