The main contribution of this work is the proposal and hardware implementation of an algorithm for the time synchronization of orthogonal frequency division multiplexing (OFDM) modulation with Hermitian symmetry for visible light communications (VLC) systems, using only the real component of the transmitted signal. OFDM systems with Hermitian Symmetry are able to satisfy the high data rates demanded by many VLC systems, as well as deal with inter-symbol interference (ISI). However, these systems are characterized by being very vulnerable to synchronization problems in both time and frequency. Time synchronization being the most critical. In this paper, a novel time synchronization technique for OFDM systems with Hermitian Symmetry is proposed. This technique is based on the inclusion of a post-FFT synchronization stage to achieve time synchronization with one-sample precision. For this purpose, the relationship that exists between an offset in the frequency domain with an offset in the time domain is used, and with this information the correction of the frequency offset from the time domain is performed. An original and novel algorithm has been designed and implemented in hardware, which uses the cyclic prefix (CP) elimination stage to perform the time correction. The performance validation of the proposed technique is done with the implementation, using the ZYBO™ development board, of a complete OFDM system applied to a real VLC system.

Orthogonal frequency-division multiplexing (OFDM) systems have been widely implemented in guided and non-guided communications. Even though they are becoming a standard for popular technologies such as WiFi, their implementation in newly emerging ones is still in evolution. As the number of connected devices increases, the radio frequency (RF) channel gets crowded. Here is where the visible light communication (VLC) links gain interest. VLC offers a wireless alternative to RF with a trade-off between the necessity of line of sight with the offer of a free, highly secure, and immune to electromagnetic interference communication channel. Therefore, the characterization and implementation of new techniques that can solve this kind of channel's particularities will help the technology achieve the maximum of its capacities. This paper proposes a programmable software implementation of an OFDM system using a novel phase correction technique for VLC channels. The new equation takes into account two types of phase shifts, one that will be non-deterministic (has a random variation) and another that will be deterministic and, therefore, can be estimated and corrected. This second can be split into two: one that comes from the clock differences and has more impact on higher subcarriers, and the second that appears from the electronics of the link and will directly impact the symbols' phase. The main difference with current phase correction techniques is the identification and estimation of the deterministic noise specific to VLC systems. The deterministic noise impact all subcarriers equally and must be subtracted before the measure of the shift induced by the differences between the transmitter and receiver clocks. Another difference is that the analysis and tests have been done with data collected in an actual hardware implementation.

This paper presents an FPGA-based feasibility study of the main digital processing blocks required for future real-time Visible Light Positioning (VLP) receivers. The study focuses on the physical hardware implementation and modular validation of two key components: a Sliding Discrete Fourier Transform (SDFT) pre-processing stage for sinusoidal carrier magnitude extraction and a hardware-optimized Multi-Layer Perceptron (MLP) inference engine for coordinate estimation. The positioning model is trained and evaluated using experimental data acquired from a high-accuracy VLP setup, whereas the FPGA validation is performed at module level on a physical Visible Light Communication (VLC) hardware platform. Therefore, the reported spatial positioning accuracy corresponds to the offline VLP reference dataset, while the FPGA results quantify numerical fidelity, latency, and resource utilization of the implemented hardware blocks. The design was implemented on a Xilinx^® Zynq-7000 (xa7z020clg484-1Q) device and operated at 100MHz. The SDFT block requires 61658clock cycles, corresponding to 616.58µs, while the MLP variants require between 606and 6612 clock cycles, corresponding to 6.06µs and 66.12µs, respectively. All MLP implementations reproduce the offline software reference with HW/SW MSE values on the order of 10⁻⁶, confirming FPGA numerical fidelity rather than end-to-end positioning accuracy. The results show that the proposed SDFT and MLP hardware blocks constitute viable building blocks for future FPGA-based VLP receivers, while also identifying the remaining integration steps required for a complete end-to-end real-time system.

This paper presents an FPGA feasibility study of two digital processing blocks for a future real-time Visible Light Positioning (VLP) receiver: a Sliding Discrete Fourier Transform (SDFT) stage for carrier-magnitude extraction and a hardware-optimized Multi-Layer Perceptron (MLP) inference engine for coordinate estimation. The localization model is trained and evaluated offline with experimental data from the four-photodiode VLP system reported in the reference work, whereas the SDFT and MLP FPGA blocks are validated separately on a physical Visible Light Communication (VLC) hardware platform. Therefore, the reported 1–2 mm spatial accuracy belongs to the offline reference dataset and model, whereas the FPGA results quantify module latency, numerical fidelity, implementation resources, and tool-estimated power, not physical end-to-end coordinate accuracy. The design was implemented on a AMD Xilinx Zynq-7000 (xa7z020clg484-1Q) SoC FPGA device and operated at 100 MHz. The SDFT block requires 61,655 clock cycles, corresponding to 616.55 μs, while the MLP variants require between 607 and 6612 clock cycles, corresponding to 6.07 μs and 66.12 μs, respectively. All MLP implementations reproduce the offline software reference with HW/SW MSE values on the order of ${10}^{-6}$. The resulting blocks and the reported first HLS integration estimates establish an implementation path while identifying the acquisition, synchronization, and multi-tone validation work still required for a complete receiver.