To improve the tradeoff between dynamic breakdown voltage (BV_dyn) and specific on-resistance (R_on,sp) in SOI LDMOS devices, a double-step-doped SOI LDMOS with a P-type buried layer (DSD-PBL SOI LDMOS) is proposed. The device incorporates a double-step-doped (DSD) drift region and a uniformly doped P-type buried layer (PBL) beneath the buried oxide (BOX). The DSD drift region and the PBL jointly modulate the electric-field distribution, enabling a high drift-region doping concentration while preserving the breakdown capability. Simulation results show that the proposed device achieves a BV_dyn of 678 V, which is comparable to the 680 V obtained by the step-doped SOI LDMOS (SD-SOI LDMOS) with the same DSD drift region and higher than the 605 V obtained by the conventional SOI LDMOS (C-SOI LDMOS). Meanwhile, the proposed device has a R_on,sp of 7.84 Ω⋅mm², corresponding to reductions of 39.0% and 45.6% compared with the SD-SOI LDMOS and C-SOI LDMOS devices, respectively. Under identical switching and thermal-management conditions, the reduced R_on,sp results in lower conduction losses and improved thermal performance.