In the standalone renewable energy system, multiport converter is more desirable than several single-input converters as it has advantages of simpler circuit, higher efficiency and lower cost. This paper proposes a novel topology synthesis method to derive integrated three-port converters with low cost and compact structure. With the proposed topology synthesis method, integrated three-port converters can be easily developed from conventional single-input single-output (SISO) converters by replacing a switch and a diode with a basic cell including bidirectional power flow. Compared with the SISO converter, the derived integrated three-port converters only need to add the extra switch and diode, which makes they have low cost and compact structure. As an example, topology synthesis based on buck, boost, buck-boost, Cuk, SEPIC, and zeta converters is performed in this paper. The proposed topology synthesis method can also be extended to deduce a series of N-port converters. In order to achieve better understanding of the proposed converters, the integrated three-port SEPIC converter is specifically analyzed, including its operation principle, steady-state performance, small-signal modeling and control system. Finally, experimental verifications have been carried out to illustrate the feasibility and effectiveness of the proposed topology synthesis method.

This article proposes a two-mode active balancing circuit for series-connected cell strings. The proposed balancing circuit has two operation modes: any cell to any cell (AC2AC) and direct cell to cell (DC2C) modes. In AC2AC mode, the balancing circuit can be equivalent to an improved switched-capacitor (SC) balancing circuit, and the energy is transferred among all imbalanced cells, implementing the higher balancing speed when the voltage gap between cells and the number of imbalanced cells are large. In DC2C mode, the proposed balancing circuit can be equivalent to a balancing circuit based on three-resonant-state LC unit, and the energy is transferred from the highest voltage cell to the lowest voltage one, achieving the higher balancing efficiency and speed as well as accuracy when the voltage gap between cells is small. The operation state, balancing power, and balancing efficiency of each mode are analyzed in detail. The control strategy and design considerations of the balancing circuit are introduced to obtain the optimal balancing performance. Experimental results are provided to verify the validity of the proposed balancing circuit. The results show that the proposed balancing circuit achieves high balancing accuracy and efficiency as well as balancing speed.

In order to eliminate the voltage imbalance among battery cells when they are connected in series, the paper proposes a double-layer E-structure (DLE) equalizer based on bidirectional buck–boost converters, which has the advantage of quick equalization speed and can be applied to arbitrary number batteries. Furthermore, a novel two-stage equalization control strategy is proposed for the DLE equalizer to decrease maximum voltage gap between the maximum and minimum voltage cells. The paper analyses the working principle of proposed equalizer in detail and describes the detailed design of the control strategy and implement process. Simulation and experiment results show that the proposed equalizer can improve equalization performance of battery cells compared with adjacent cell-to-cell (AC2C) equalizer.

The existing series-parallel switched-capacitor (SPSC) equalizers have a high voltage stress on switch, which reduces the reliability of the equalizer. To overcome this problem, an automatic voltage equalizer based on switched-capacitor for serial cells is proposed in this paper. In the proposed equalizer, the maximum switch-voltage-stress is significantly abated compared with existing SPSC equalizers, which enhances the equalization reliability. This proposed equalizer also shortens the length of equalization path between cells, which increases the speed of the equalizer. The equalization speed in this proposed equalizer is analyzed concretely, and design considerations are proposed. Simulation as well as experimental results are presented to verify the validity of this proposed equalizer.