Due to its low loss and high switching frequency, the silicon carbide metal oxide field effect transistors (SiC MOSFETs) are more suitable as switching devices in power inverter for electric vehicles (EVs). However, the power losses of power inverter would be dramatically increased with the rise of switching frequency, which would result in the limitation of using the high switching frequency performance of SiC MOSFET. In view of this case, this paper would systematically analyze the power losses distribution of power inverter and further optimize its efficiency under the high switching frequency. It is demonstrated that the power losses of power inverter are linearly increased with the rise of switching frequency, which is mainly caused by the switching losses of MOSFET chips increment. Based on this situation, an adaptive discontinuous pulse width modulation (ADPWM) is proposed to optimize the power inverter efficiency under the high switching frequency, which can effectively reduce the total power losses of power inverter and improve its efficiency compared with that of the conventional PWM strategies. Finally, the power losses and efficiency of power inverter with the proposed ADPWM strategy is verified by the experimental results.

Thermal stress is one of the most important factors leading to power module failure. Under the load condition of high current with low fundamental frequency or largely changed load current, it would cause high junction temperature swing amplitude (JTSA) of chips, which could accelerate the failure of power module. To address this issue, this paper proposes a dual fuzzy logic controller‐based active thermal control (ATC) strategy to reduce the JTSA of chips in cases of variable power profiles. Two fuzzy logic controllers are designed to reduce the JTSA of chips by adjusting the switching frequency and pulse width modulation (PWM) strategy, respectively. One fuzzy logic controller is designed to reduce the transient JTSA of chips, which is done by changing the switching frequency according to the fundamental frequency and transient JTSA. The other one is to reduce the mean JTSA of chips, which is implemented by regulating the switching frequency and PWM modes according to the mean junction temperature and its variation. The minimum one is selected as the switching frequency of power inverter. Finally, the effectiveness of the proposed ATC strategy is verified by simulation and experimental results.

As a power hardware-in-the-loop (PHIL) technology, the power-stage motor emulator (ME) can be employed for the port characteristics emulation of motors. Meanwhile, the ripple current reproduction is one of the key technologies for achieving the high precision emulation of the port characteristics. Commonly, the high requirement for the hardware topology and the modulation strategy with rapid response and low harmonics are the main challenges. Aiming to obtain the precision ripple current, a ME scheme with dual-branch parallel topology is proposed in this paper, of which the equivalent switching frequency can be increased greatly by mean of interleaving switch. Furthermore, a new three-level space vector modulation strategy based on the idea of virtual transformation is presented. With the proposed strategy, the dual-branch parallel topology can be equivalently transformed into a specific three-phase three-level back-to-back topology. Finally, simulation and bench experiments have been conducted to validate the effectiveness of the proposed scheme. The results indicate that the proposed topology combined with the modulation strategy has a superior performance in improving the ripple current tracking accuracy of ME. Moreover, the proposed method can provide an excellent insight into improving the emulation accuracy of motor characteristics in practical applications.