Deep neural networks (DNNs) have surpassed other algorithms in analyzing today’s abundant data. Due to the security and delay requirements of the given applications, analytical data extraction should happen on edge devices. Edge devices, however, struggle to support the increasingly complex DNNs because of the models’ high computational load and number of employed parameters. Thus, edge devices need support by efficient accelerators to process DNNs. However, the design of DNN accelerators remains challenging, as there is a lack of established design techniques directed towards a specific design point in terms of energy budget, area, time-to-solution, and classification accuracy. This paper fills this gap by providing a quantitative, large-scale, state-of-the-art comparison of DNN accelerators building on published data subjected to technology scaling and benchmark normalization. The leveled comparison stimulates learning from previous designs by considering the impact of each technique on energy, area, and time-to-solution. Furthermore, the key design techniques used in the DNN accelerators are classified according to their influence on the classification accuracy. Finally, we provide a discussion of hardware accelerators to support future designers in considering the trade-off between efficiency and accuracy in order to identify the most suitable techniques for certain benchmarks.

Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down over the last forty years making possible the design of high-performance applications, following the predictions made by Gordon Moore and Robert H. Dennard in the 1970s. However, there is a growing concern that device scaling, while maintaining cost-effective production, will become infeasible below a certain feature size. In parallel, emerging applications including Internet-of-Things (IoT) and big data applications present high demands in terms of storage and computing capability, combined with challenging constraints in terms of size, power consumption and response latency. In this scenario, memristive devices have become promising candidates to complement the CMOS technology due to their CMOS manufacturing process compatibility, great scalability and high density, zero standby power consumption and their capacity to implement high density memories as well as new computing paradigms. Despite these advantages, memristive devices are also susceptible to manufacturing defects that may cause unique faulty behaviors that are not seen in CMOS, increasing significantly the complexity of test procedures. This paper provides a review about the manufacturing process of memristives devices, focusing on Valence Change Mechanism (VCM)-based memristive devices, and a comparative analysis of the CMOS and memristive device manufacturing processes. Moreover, this paper identifies possible manufacturing failure mechanisms that may affect these novel devices, completing the list of the already known mechanisms, and provides a discussion about possible faulty behaviors. Note that the identification of these mechanisms provides insights regarding the possible memristive devices’ defective behaviors, enabling to derive more accurate fault models and consequently, more suitable test procedures.

The computation of the brain relies on the highly efficient communication among billions of neurons. Such efficiency derives from the brain’s plastic and reconfigurable nature, enabling complex computations and maintenance of vital functions with a remarkably low power consumption of only ∼20 W. First efforts to leverage brain-inspired computational principles have led to the introduction of artificial neural networks that revolutionized information processing and daily life. The relentless pursuit of the definitive computing platform is now pushing researchers towards investigation of novel solutions to emulate specific brain features (such as synaptic plasticity) to allow local and energy efficient computations. The development of such devices may also be pivotal in addressing major challenges of a continuously aging world, including the treatment of neurodegenerative diseases. To date, the neuroelectronics field has been instrumental in deepening the understanding of how neurons communicate, owing to the rapid development of silicon-based platforms for neural recordings and stimulation. However, this approach still does not allow for in loco processing of biological signals. In fact, despite the success of silicon-based devices in electronic applications, they are ill-suited for directly interfacing with biological tissue. A cornucopia of solutions has therefore been proposed in the last years to obtain neuromorphic materials to create effective biointerfaces and enable reliable bidirectional communication with neurons. Organic conductive materials in particular are not only highly biocompatible and able to electrochemically transduce biological signals, but also promise to include neuromorphic features, such as neuro-transmitter mediated plasticity and learning capabilities. Furthermore, organic electronics, relying on mixed electronic/ionic conduction mechanism, can be efficiently coupled with biological neural networks, while still successfully communicating with silicon-based electronics. Here, we envision neurohybrid systems that integrate silicon-based and organic electronics-based neuromorphic technologies to create active artificial interfaces with biological tissues. We believe that this approach may pave the way towards the development of a functional bidirectional communication between biological and artificial ‘brains’, offering new potential therapeutic applications and allowing for novel approaches in prosthetics.

Wireless Sensor Nodes (WSN) have a wide range of applications in health care and life style monitoring. Their severe energy constraint is often addressed through minimizing the amount of transmitted data by way of energy-efficient on-node signal processing. The rationale for this approach is that a large portion of WSN energy is consumed by the radio communication even for very low-data-rate situations [1]. Efficient on-node processing has been the subject of recent work, with the common element being aggressive voltage scaling into the sub-threshold region [2-4]. A major assumption of the existing works is that the amount of required computation is low, justifying an on-node processor with limited computational capability. While this might be the case for many applications of WSNs, emerging ambulatory biomedical signal processing applications exceed the performance offered by today's on-node processors.

This paper identifies novel directions of standard-cell-based synthesizable memory design. A compact 18T-bitcell of OR-AND-Invert (OAI) and AND-OR-Invert (AOI) logic gates is presented with bit-selective write and multiplexed read accesses. It reduces the bitcell area by 11%-40% compared to the state-of-the-art clock-gating-based D-latch schemes while avoiding custom-cell design. The improved storage density comes from the tight integration on two levels-coupling the read multiplexing within each bitcell and taking advantage of structured datapath placement in bitcell arrays by using commercial CAD tools. As measured on a 40 nm SRAM of 90 kb, the OAI/AOI-gate-based synthesizable memory features 0.4 V minimum access voltage, 30 fJ minimum read energy per bit, and a leakage power of 1.4 pW per bit at 0.3 V data retention voltage. It is ideally suited for IoT-node design operating in sub-Vt for joint dynamic energy and leakage power reduction. Further, it enables fast turn-around times by IP reuse over technology nodes with minimal (re)design effort.