In grid interactive power converter applications, phase locked loop (PLL) algorithms are very important to realize grid synchronization. The performance of PLL should not be affected by adverse conditions such as voltage unbalance, harmonics, frequency and phase changes. Otherwise, synchronization errors occur between the grid interactive inverter and the grid. In this paper, two different PLL algorithms are simulated by modeling under MATLAB/Simulink. The performances of the PLLs are comparatively presented under four different grid conditions such as balanced, unbalanced, harmonics and variable frequency. In this study, synchronous reference frame-PLL (SRF-PLL) and decoupled double synchronous reference frame-PLL (DDSRF-PLL) which are mostly used, state-of-arts and effective PLL algorithms are analyzed by modeling in grid synchronization applications. It has also been demonstrated the positive and negative aspects of the PLLs based on the obtained results.

Quasi type-1 phase-locked loop (QT1-PLL) has become very popular in recent times for grid-connected converters owing to its simple structure and fast dynamic response. By means of the use of a half-cycle moving average filter (MAF), this PLL can completely eliminate all the nominal frequency odd-order harmonics. However, the performance deteriorates when the grid experiences frequency drift. To address this issue, high-order non-adaptive MAF with the same window length has been proposed in the literature. Although it improves the off-nominal frequency performance, the filtering induced phase-lag remains the same. To address this issue, high-order delayed signal cancellation technique is considered in this study. The proposed technique demonstrates similar filtering performance as high-order MAF, however, by using lower window length. This makes the proposed technique fast responsive with lower memory requirement compared to similar other techniques in the literature. Detailed small signal modelling and associated parameter tuning method are established to facilitate the implementation of the proposed method inside current controllers of grid-connected converters. Comparative experimental results are provided with QT1-PLL and third-order QT1-PLL (TQT1-PLL) to illustrate the suitability and performance enhancement by the proposed method. These results show that in addition to the superior filtering capability of the proposed PLL, its settling-time is less than one cycle of nominal frequency under most grid conditions. Consequently, in terms of enhancing the dynamic response of the QT1-PLL, the proposed HDSC-PLL is superior to the TQT1-PLL.

In this study, an advanced phase‐locked‐loop (PLL), which has a simple structure and a low computational burden is proposed. The proposed PLL also improves the dynamic performance and the filtering capability of the conventional three‐phase enhanced‐PLL (3pEPLL) significantly. The conventional 3pEPLL operates three individual EPLL blocks for each phase voltage and a fourth EPLL for estimation of the magnitude, frequency, and phase angle, which considerably increases the structural complexity and computational burden. However, the proposed PLL called enhanced‐3pEPLL (E ² PLL) employs only two single‐phase EPLL modules in its pre‐filtering stage. A moving‐average‐filter (MAF) is also supplemented on the error signal path of these EPLL modules, which allows smoother estimation of the magnitude, frequency, and phase angle, and improves the filtering capability of the EPLLs. Unlike the conventional 3pEPLL, the proposed E ² PLL employs a quasi‐type‐1 PLL (QT1‐PLL) to estimate the magnitude, frequency, and phase information of the fundamental grid voltage. The structure of QT1‐PLL is similar to a type‐1 PLL, which offers a low transient response time. The small‐signal model of the proposed PLL is derived for stability analysis and parameter design procedure. The effectiveness of the E ² PLL is verified owing to experimental results and comparison with the conventional 3pEPLL and QT1‐PLL.