This letter investigates the possibility to replace numerical TCAD device simulations with a multi-layer neural network (NN). We explore if it is possible to train the NN with the required accuracy in order to predict device characteristics of thousands of transistors without executing TCAD simulations. Here, in order to answer this question, we present a hierarchical multi-scale simulation study of a silicon junctionless nanowire field-effect transistor (JL-NWT) with a gate length of 150 nm and diameter of an Si channel of 8 nm. All device simulations are based on the drift-diffusion (DD) formalism with activated density gradient (DG) quantum corrections. For the purpose of this letter, we perform statistical numerical experiments of a set of 1380 automictically different JL-NWTs. Each device has a unique random distribution of discrete dopants (RDD) within the silicon body. From those statistical simulations, we extract important figures of merit (FoM) such as OFF-current (I _OFF ) and ON-current (I _ON ), subthreshold slope (SS), and voltage threshold (V _TH ). Based on those statistical simulations, we train a multi-layer NN and we compare the obtained results with a general linear model (GLM). This shows the potential of using NN in the field of device modeling and simulation with a potential application to significantly reduce the computational cost.

We present charge state transition levels of 23 intrinsic defects and dopant substitutions in the compound III-V semiconductor ${\mathrm{In}}_{0.53}{\mathrm{Ga}}_{0.47}\mathrm{As}$, calculated with density functional theory. We also report the Shockley-Read-Hall (SRH) recombination rate and capture coefficients for defects found to have deep trap levels. Our calculations show that seven of the considered defects exhibited deep trap levels capable of acting as electron and hole traps in devices: the ${\mathrm{As}}_{\text{In/Ga}}$ antisites, the ${\mathrm{V}}_{\text{In/Ga}}$ vacancies, the ${\left(\text{In/Ga}\right)}_{\text{As}}\text{−}{\mathrm{As}}_{\text{In/Ga}}$ double antisites, and the ${\mathrm{Sn}}_{\text{As}}$ substitution. We found that the ${\mathrm{As}}_{\text{In}}$ antisite exhibits the highest electron-capture coefficient of $C_n=2.2\times {10}^{-5}{\mathrm{cm}}^3{\mathrm{s}}^{-1}$ at room temperature. The defect with the highest hole-capture coefficient was found to be the ${\mathrm{In}}_{\text{As}}\text{−}{\mathrm{As}}_{\text{In}}$ double antisite, with $C_p=3.4\times {10}^{-6}{\mathrm{cm}}^3{\mathrm{s}}^{-1}$. Furthermore, this defect also causes the highest recombination rate in the intrinsic semiconductor, owing to its likewise relatively large electron-capture coefficient. The defects which are most likely to occur are argued to be the antisites, due to their low formation energies and matching transition levels with experiments. Additionally, it is found that the ${\mathrm{Sn}}_{\text{As}}$ substitution also causes a significant recombination in the semiconductor, but it is argued to only be of importance at very high doping levels.