The configuration of the active gate driver (AGD) significantly impacts how well power semiconductor devices work and how efficient they are. This research presents a new AGD single chip design that identifies the Miller plateau when the signal is turning on and off by utilizing a two-level Miller detector precisely. Moreover, it includes a power gating mechanism to lower the AGD’s power usage. Furthermore, it comes with an Equalizer to guarantee the best use of all MOS devices in the buffer arrays. It is fabricated using TSMC 180-nm High Voltage Bipolar-CMOS-DMOS (HV BCD) process. By conducting thorough measurements across various conditions, its functionality was confirmed at an operating frequency of 500 kHz. Based on the measurement results, the average total power dissipation with power gating is 787 mW. In addition, its power gating mechanism shows a notable decrease of 10% in static power dissipation.

Recent digital pulsewidth modulation (DPWM) researches use multiple clock inputs and long D flip-flop (DFF) arrays, which makes scaling to different DPWM frequencies challenging. This brief demonstrates a DPWM that utilizes a single clock and a Matrix shift array, allowing it to be scaled to any frequency and reducing the effects of clock skew. It has a clock gating technique that selects a specific row of DFFs based on the required % duty cycle. The DPWM design has a dead time generator to prevent shoot-throughs. The DPWM has been fabricated using UMC 180-nm CMOS process. The performance and functionality of the DPWM have been verified through the measured comparisons of % duty ratio, dead time ( $T_{dt}$ ), and output frequency ( $f_{\text {out}}$ ) at input clock frequency ( $f_{\text {clk}_{\text {in}}}$ ) equal to 10 $\sim $ 100 MHz. The DPWM design has a maximum % duty ratio of 90.6%, $T_{dt}$ = 1.8 ns, and $f_{\text {out}}$ = 6.25 MHz with 3.4-mW power consumption at $f_{\text {clk}_{\text {in}}}$ = 100 MHz.