This paper investigates the Fault Ride Through (FRT) capability improvement of a Doubly Fed Induction Generator (DFIG) wind turbine using a Dynamic Voltage Restorer (DVR). Series compensation of terminal voltage during fault conditions using DVR is carried out by injecting voltage at the point of common coupling to the grid voltage to maintain constant DFIG stator voltage. However, the control of DVR is crucial in order to improve the FRT capability in DFIG based wind turbines. The reported DVR verifies the use of a combined Feed-Forward and Feed-Back (CFFFB) based voltage control to obtain both good transient and steady-state responses. The improvement in performance of DVR using CFFFB control compared to the conventional Feed-Forward control is observed in terms of voltage sag mitigation capability, active and reactive power support without tripping, DC-link voltage balancing and fault current control. The advantage of utilizing this combined control is verified through MATLAB/Simulink based simulation results using 1.5 MW grid connected DFIG based wind turbine. The results show good transient and steady-state response and good reactive power support during both balanced and unbalanced fault conditions.

In this study, a new multilevel inverter configuration which introduces a combination of cascaded H‐bridge multilevel inverter with a double level circuit is proposed. The double level circuit is a half‐bridge inverter when combined with a cascaded H‐bridge multilevel inverter, will increase the output voltage level to nearly twice that of a conventional cascaded H‐bridge multilevel inverter. The effectiveness of the proposed configuration is demonstrated with five different cases of cascaded H‐bridge multilevel inverter configurations. Phase disposition carriers arrangement with sinusoidal reference has been utilised in pulse width modulation for generating the gating signal of switches to achieve high‐quality output voltage waveform. A comparison is carried out with different parameters such as %total harmonic distortion, distortion factor, the maximum voltage step of output voltage level and peak inverse voltage. Analysis of power loss and theoretical calculation of %total harmonic distortion is described. Also, a new method for calculating the overall component count is discussed. As a result, the proposed configuration requires lesser component count for generating higher output voltage level with lower %total harmonic distortion. Selected simulation and experimental results are shown to verify and validate the proposed multilevel inverter configuration.

This paper proposes a new multilevel inverter (MLI) topology that utilizes trinary sequence for the dc sources. It gives maximum output voltage level with minimum dc source and switch count when compared to other sequences such as symmetric, natural, binary and quasi-linear. This is due to the fact that the trinary sequence generates of all additive and subtractive combinations of input dc levels in the output voltage waveform. The concept is implemented on a 9-level asymmetric MLI using only four active devices. Multicarrier unipolar pulse width modulation technique is adopted to create the switching pulses. Theoretical calculation of total harmonic distortion in both voltage and current waveforms has been performed using asymptotic time domain formula. These values are compared with simulation and experimental values for different modulation indices. Power loss calculation for proposed topology is discussed with appropriate mathematical equations.