Static random access memory (SRAM) is the most commonly employed semiconductor in the design of on-chip processor memory. However, it is unlikely that the SRAM technology will have a cell size that will continue to scale below 45 nm, due to the leakage current that is caused by the quantum tunneling effect. Magnetic random access memory (MRAM) is a candidate technology to replace SRAM, assuming appropriate dimensioning given an operating threshold voltage. The write current of spin transfer torque (STT)-MRAM is a known limitation; however, this has been recently mitigated by leveraging perpendicular magnetic tunneling junctions. In this article, we present a comprehensive comparison of spin transfer torque-MRAM (STT-MRAM) and SRAM cache set banks. The non-volatility of STT-MRAM allows the definition of new instant on/off policies and leakage current optimizations. Through our experiments, we demonstrate that STT-MRAM is a candidate for the memory hierarchy of embedded systems, due to the higher densities and reduced leakage of MRAM.We demonstrate that adopting STT-MRAM in L1 and L2 caches mitigates the impact of higher write latencies and increased current draw due to the use of MRAM. With the correct system-on-chip (SoC) design, we believe that STT-MRAM is a viable alternative to SRAM, which minimizes leakage current and the total power consumed by the SoC.

Physically unclonable functions (PUFs) are one of the most important breakthrough for security of devices as they represent a low-cost means to provide authentication and secure storage. PUFs measure nano-scale mismatches that are inherently caused by the manufacturing process. However, the mechanisms exploited by PUF circuits depend on the working conditions, such as temperature, device aging, and current flow, making them unreliable and, hence preventing their wider employment. One of the most investigated PUF exploits pairs of ring oscillators (ROs): frequencies measured from each pair are compared for extracting one response bit. However, extracted bit-strings are not suitable for authentication purposes as they may change during time. In this paper, we propose a new identification mechanism, based on ROs, which is immune to aging and working conditions. Through a mathematical demonstration and an extensive experimental campaign, which involved real field programmable gate array devices, we demonstrate its ability to reliably accomplish identification of silicon devices.

We will present a survey of trends in the semiconductor industry for programmable hardware. The main objective of this paper is educational and the focus is FPGAs and its related or vs technologies which have emerged mostly in the second half of the last decade. We will try to analyze what were the prominent reasons for emerging of these technologies. What are the advantages and drawbacks of them, what makes FPGAs still most dominant in this area and will it be same or change in future. FPGAs themselves during this time have dramatically changed and the classical term FPGA does not fully characterize in name what FPGAs have actually become now. These changes and the continuing rising strength of multicore and ultimate power consumption challenge in industry will have what impact. Will these technologies collide or co-exist in future (nobody in industry or academics knows that and it is hard to predict). We will try to present the distinguishing technical and commercial potentials of different technologies which give an edge of one over the other.

This paper investigates heavy ion irradiation effects on Perpendicular Magnetic Anisotropy Spin Transfer Torque Magnetic Tunnel Junction devices (PMA STT-MTJ). The Radiative campaign took place at the Université Catholique de Louvain (UCL) facility. The considered devices consist of STT p-MTJs purely magnetic memories and they were fabricated at SPIN-TEC using the most advanced CoFeB-MgO MTJ technology. Single-event upset (SEU) tolerance and modification of magnetic properties has been investigated.

Electro-Magnetic Analysis has been identified as an efficient technique to retrieve the secret key of cryptographic algorithms. Although similar mathematically speaking, Power or Electro-Magnetic Analysis have different advantages in practice. Among the advantages of EM Analysis, the feasibility of attacking limited and bounded area of integrated systems is the key one. Within this context, the contribution of this paper is a countermeasure against local EM attack performed with tiny magnetic probes. The basic idea is to design circuits such that all datapaths and D-type Flip-Flops, involved in the computation of intermediate values of cryptographic elements, randomly change within a set of logically equivalent electrical paths that are spatially distributed within the Integrated Circuit (IC) die.