Industrial Internet of Things (IIoT) has emerged as a prospective technology that improves the productivity and automation level for industrial applications. Devices from cooperative IIoT domains will communicate and collaborate on the increasingly complicated manufacturing tasks. To secure cross-domain device collaborations, we propose combining the blockchain with multifactor authentication. Because the multifactor authentication conforms to IIoT devices’ operation modes and brings higher security levels, and the blockchain technology contributes to building trust among different domains. However, this combined usage still has limitations in terms of the potential loss of factor attack, the storage overhead on the blockchain, and the contradiction between efficiency and privacy preservation. Motivated by these facts, in this article, we develop a privacy-preserving blockchain-based multifactor device authentication protocol for cross-domain IIoT. Specifically, multiple factors are additionally encoded by the hardware fingerprint into random numbers, before being transformed into key materials. The blockchain only stores each domain’s dynamic accumulator, which accumulates derived key materials for devices, thereby reducing the overhead. Moreover, the on-chain accumulator is leveraged to efficiently verify the unlinkable identities of cross-domain IIoT devices. The security of our protocol is formally proved, and the security features and functionalities are, respectively, discussed. A proof-of-concept prototype was implemented to prove the efficiency and reliability. The comparison results indicate that the on-chain storage is greatly reduced. Finally, the smart contract’s performance was evaluated to show scalability.

Reconfigurable digital filter is being widely used in applications such as communication and signal processing. Its performance, power consumption, and logic resource utilization are the major factors to be taken into consideration when designing the filters. This paper proposes a concise canonic signed digit coefficient grouping method aiming at reducing the number of common subexpressions (CSs). Further, we statistically analyze every CS occurance for numerous sorts of the finite-impulse response (FIR) filters and obtain characterization of the distribution behavior for all the possible CS patterns in a 16-bit coefficient. Thus, a novel processing element structure is proposed to form a medium-grain array for computationally efficient realization of reconfigurable FIR filter. The experiment results suggest such design implementations typically achieve 21% reduction in silicon area, 20% decrease in power consumption, and 14% improvement in operation speed in comparison to other conventional FIR architectures.

The authentication of Internet of Things (IoT) devices based on the Physical Unclonable Function (PUF) is widely adopted in the information security domain. However, the leakage of PUF responses in an authentication system reduces its privacy and security. To improve its security, we can utilize the Elliptic Curve Cryptography (ECC) algorithm with different key lengths to encrypt the PUF response arbitrarily. Point multiplication is the most time-consuming operation in ECC because of its complex calculation process, which seriously affects the efficiency of the PUF response encryption. In order to solve this problem, a point multiplier based on binary field with reconfigurable key lengths of 233, 283, 409 and 571 is designed in this paper. In our method, by reusing the underlying computing units, the resources needed for point multiplication are effectively reduced. What it is more innovative is that double point multiplication operations with a key length of less than 283 bits can be performed simultaneously in the elaborate designed point multiplication circuit, which can effectively speed up the encryption process of ECC. The circuit is implemented on Xilinx Virtex-6 FPGA. The experiment results show the single point multiplication times of 233, 283, 409 and 571 key lengths are 19.33, 22.36, 41.36 and 56.5 μs, respectively, under the clock frequency of 135 MHz. In addition, it only needs 19.33 μs to perform two-point multiplication operations when the key length is 233 bits at the same time. When the key length is 283 bits, the point multiplication operation can be performed twice in 22.36 μs.

FPGA-based SoCs have been gaining great favors among traditional applications and expanding the application domains to some new areas. Reusing and sharing components is an attractive and pratical methodology for system designers to reduce the design complexity of the SoC architectures. Open source hardware has become an effective method of improving the design productivity. As the core functional component, processors affects the performance of SoC systems. This paper investigates existing open source processors, and gives an overview. From the points of usability and stability, the main features of open source processors are summarized. Following these features, some open source processors with high usability and stability are selected. These open source processors and existing vendor-provided soft processors are implemented on Stratix V and Virtex-7 FPGAs using corresponding EDA tools, Quart us n and ISE. The implementation results are compared and discussed.

This study establishes a multi-source fault identification method based on a combined deep learning strategy to identify a multi-source fault effectively in the fault diagnosis of complex industrial systems. This framework is composed of feature extraction and classifier design. In the first state, the signal is transformed to the time-frequency domain and the time-frequency feature is learned using stacked denoising autoencoders. A learning method that consists of unsupervised pre-learning and supervised fine-tuning is used to train this deep model. In the second state, a model for an ensemble multiple support vector machine classifier is created to recognize fault information. Ten types of rolling bearing signals were adopted in a simulation experiment to validate the effectiveness of the proposed framework. The results demonstrate that the joint model helps to obtain higher recognition accuracy.