Field-effect transistors based on two-dimensional (2D) materials have the potential to be used in very large-scale integration (VLSI) technology, but whether they can be used at the front end of line or at the back end of line through monolithic or heterogeneous integration remains to be determined. To achieve this, multiple challenges must be overcome, including reducing the contact resistance, developing stable and controllable doping schemes, advancing mobility engineering and improving high-κ dielectric integration. The large-area growth of uniform 2D layers is also required to ensure low defect density, low device-to-device variation and clean interfaces. Here we review the development of 2D field-effect transistors for use in future VLSI technologies. We consider the key performance indicators for aggressively scaled 2D transistors and discuss how these should be extracted and reported. We also highlight potential applications of 2D transistors in conventional micro/nanoelectronics, neuromorphic computing, advanced sensing, data storage and future interconnect technologies.

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators.

One of the most important degradation modes in CMOS technologies, the bias temperature instability (BTI) has been known since the 1960s. Already in early interpretations, charge trapping in the oxide was considered an important aspect of the degradation. In their 1977 paper, Jeppson and Svensson suggested a hydrogen-diffusion controlled mechanism for the creation of interface states. Their reaction-diffusion model subsequently became the dominant explanation of the phenomenon. While Jeppson and Svensson gave a preliminary study of the recovery of the degradation, this issue received only limited attention for many years. In the last decade, however, a large number of detailed recovery studies have been published, showing clearly that the reaction-diffusion mechanism is inconsistent with the data. As a consequence, the research focus shifted back toward charge trapping. Currently available advanced charge-trapping theories based on switching oxide traps are now able to explain the bulk of the experimental data. We give a review of our perspective on some selected developments in this area.

Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry^1,2. However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm²) devices on unfunctional SiO₂–Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm²) interconnection³ and as a channel of large transistors (roughly 16.5 µm²) (refs. ^4,5), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D–CMOS hybrid microchips for memristive applications—CMOS stands for complementary metal–oxide–semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm². We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications.