Gait analysis and research have been developed to obtain characteristics of movement patterns of people while walking. However, traditional measuring systems present different drawbacks that reduce their use and application. Among those drawbacks one can find: high price, low sampling frequency and limiting number of steps to be analyzed. Traditional measuring gait systems carry out their measurement at frequencies oscillating between 60 to 100 Hz. It can be argued about the need of higher sampling rates for gait measurements. However small displacements of the knee or hip for example, cannot be seen with low frequencies required a more detailed sampling and higher frequency sampling. Bearing this in mind, in this paper is presented a 250 Hz system based on accelerometers for gait measurement, and the particularities of knee and hip angles during gait are highlighted. The system was designed with a PCI data acquisition card instrumented with an FPGA to achieve a rate sample of 250 Hz. The accelerometers were placed in thighs and legs to calculate the joint angles of hip and knee in the sagittal plane. The angles were estimated using the acceleration polygon method without integrating the acceleration and without filters. The gait of thirty healthy people of Mexican phenotype was analyzed over a flat floor free of obstacles. The results showed the gait phases and particularities associated with the walking style and people's laterality; the movement patterns were similar in the thirty persons. Based on the results, the particularities as the maximum amplitude in the angles and the shape in the movement patterns were related to the anthropometry and people phenotype. The sampling frequency was essential to record 340 samples in single gait cycle and so registering the gait cycle with its particularities. In this work were recorded an average of 8 to 10 gait cycles, and the results showed variation regarding works carried out in biomechanics laboratories; this variation was related to the method and reference frame used to obtain the joint angles and the accuracy of measurement system.

Currently, power electronics designers ask for more precise power semiconductor device models. Models based on semiconductor physics offer a better option to accomplish these requirements. Other aspect is the availability of parameter extraction methods which frequently is complicated. This paper proposes a study of parameter extraction methods for semiconductor device models. From this analysis an automatic system for semiconductor devices characterization of parameter extraction is proposed

Higher switching frequencies are required to reduce the weight and size of passive energy storing components in power electronics svstems. Switching loss reduction through soft commutation techniques such as zero-current-(ZCS) and zero-voltage switching (ZVS) is widely applied in converter designs. Test circuits are commonly used for the characterization of the switching behavior of semiconductor power devices in order to better evaluate their switching losses. This work presents the operation and design considerations of two special test circuits used for the characterization of IGBTs in ZCS commutation. The study considers the variation of important test parameters such as the hold-off time. IGBT turn-off instant, switched current, supply voltage and junction temperature.

Cascaded multilevel inverters are widely used in industry for speed control of induction motors and, even when the converters' operation is highly reliable, several faults can occur, leading to poor engine performance or even causing the whole system to stop. It is desirable to keep the system operational when a failure occurs, even when degraded, and implementing fault-tolerant systems are thus a good choice. This paper presents a general strategy for fault-tolerant control in a 7-level cascaded multilevel inverter (the faults are in semiconductor devices); the paper includes simulation and experimental results to validate the method. Los inversores multinivel en cascada son ampliamente utilizados en la industria para el control de la velocidad en motores y aun cuando los inversores son muy confiables en su operación, diversas fallas en ellos pueden ocurrir, llegando a degradar el comportamiento de los motores o incluso producirse el paro total del sistema. Cuando una falla se presenta es deseable mantener en operación el sistema aun en régimen degradado y la implementación de sistemas tolerantes a fallas en ese tipo de dispositivos son una buena opción. En este trabajo se ofrece una estrategia generalizada relativa a tolerar fallas en los dispositivos semiconductores de un inversor multinivel en cascada de siete niveles y se incluyen los resultados en simulación y experimentales para la validación del método.