PH measurements are widely used in agriculture, biomedical engineering, the food industry, environmental studies, etc. Several healthcare and biomedical research studies have reported that all aqueous samples have their pH tested at some point in their lifecycle for evaluation of the diagnosis of diseases or susceptibility, wound healing, cellular internalization, etc. The ion-sensitive field effect transistor (ISFET) is capable of pH measurements. Such use of the ISFET has become popular, as it allows sensing, preprocessing, and computational circuitry to be encapsulated on a single chip, enabling miniaturization and portability. However, the extracted data from the sensor have been affected by the variation of the temperature. This paper presents a new integrated circuit that can enhance the immunity of ion-sensitive field effect transistors (ISFET) against the temperature. To achieve this purpose, the considered ISFET macro model is analyzed and validated with experimental data. Moreover, we investigate the temperature dependency on the voltage-current (I-V). Accordingly, an improved conditioning circuit is designed in order to reduce the temperature sensitivity on the measured pH values of the ISFET sensor. The numerical validation results show that the developed solution accurately compensates the temperature variation on the measured pH values at low power consumption.

This paper presents the first behavioral model solution to the computationally efficient simulation of digital I/O buffers under overclocking operation. Our physics-based two-port approach relies on predicting the timing signals that control the activation of the driver's output stage. The identified nonlinear dynamic model operators of the input port replace the concatenated fixed step-input describing functions of the previous table-based I/O buffer information specification and of other parametric approaches. The implemented gray-box model produces more accurate results than the previous methodologies when assessing the signal integrity performance of high-speed digital links in normal and overclocking conditions under various input excitations. However, it still preserves the computational efficiency recognized for its behavioral model predecessors.

In this article, a 3-D electrothermal numerical model is used to perform the signal and thermal integrity analysis of 3-D stacked Resistive-switching random access memory (RRAM) arrays. Two main issues are found: voltage drop along the interconnects and thermal crosstalk between the memory cells. Possible solutions to these issues are here thoroughly investigated, based either on new biasing schemes or new materials. Especially, conventional nickel bars are replaced by interconnects made by copper (Cu) and carbon nanotubes (CNTs), whose electrical and thermal parameters are here described using physically based models. The analysis is performed on a 5 x 5 x 5 array, under a real case of a RESET switching, which is the worst case scenario from the electrothermal point of view. Simulation results show that the use of CNTs reduces the voltage drop in both word and bitline (BL) interconnects, thermal crosstalk, and the maximum working temperature; hence, it mitigates many of the crucial issues in the roadmap for the large-scale monolithic 3-D RRAM integration.

This paper presents a comparative synthesis of the suitability of three memristive device technologies and their corresponding spike-timing-dependent plasticity (STDP) learning windows for neuromorphic applications. The physical mechanisms behind the nonlinear switching memristive dynamics of ReRAM, based on titanium dioxide, ferroelectric tunnel junctions, and phase change memory are analyzed towards the development of accurate and computationally efficient compact models which are implemented as a Verilog-A description. The developed Verilog-A compact models are separately validated and compared with the measurement data. Moreover, the asynchronous STDP learning rule is implemented using the above mentioned memristive devices as artificial synapse for spike-based neuromorphic computing. The considered memristive technologies are compared and discussed towards their integration in fast and/or large-scale circuit implementations.

In this paper, we present a new behavioral model for high-speed digital output buffers/drivers. In the conceived model, the output current's relationship with the output voltage is expressed as a summation of a static nonlinearity plus linear dynamics. This separation in the model format is supported by the measurements as well as the physical structure of a general driver circuit. This approach merges the features of equivalent circuit and parametric approaches to build a reduced-order parametric behavioral model which, compared to other published models, is more adequate to describe the device's electrical behavior from transient input-output data. A simple single-step identification procedure is conceived to extract a model that proved to be stable and capable of significantly improving the simulation speed and accuracy of prediction. Finally, the resulting model is validated in a realistic signal integrity simulation setup, and is compared to transistor-level models and to the state-of-the-art input-output buffer information specification model.