Recently, different routing techniques were proposed for three layer clustering topology in Wireless Sensor Network (WSN) which outperform the basic two layer clustering hierarchy. The problem that remains in these approaches is the heavy control packet exchange between nodes after every round in order to choose efficient lower layer heads. Among these techniques is Hybrid Hierarchical Clustering Approach (HHCA), in which a distributed approach is proposed. According to HHCA, the upper layer heads are centrally selected by base station, while sensor nodes only have to select lower layer heads distributively. In this paper, enhanced three layer hybrid clustering mechanism is proposed that limits the exchange of control packets between nodes after every round for lower layer head selection. The energy of nodes are divided into levels upon which it is decided when nodes of a cluster need to enter into new cluster head selection phase. The proposed mechanism helps to limit control packet exchange between nodes to a large extent, at the same time keeping energy consumption between nodes balanced. Moreover, it is focused that higher layer heads are selected by base station in a manner that reduces backward transmission in the network as much as possible. Simulation results show that nodes in the proposed mechanism stay alive for a longer time as compared to other approaches, and it outperforms HHCA technique in network lifetime based on Half of the Nodes Alive (HNA) by 18 percent.

This brief presents, for the first time, a comprehensive analysis and prediction of electromagnetic interference-related common-mode (CM) noise for a 20-Gb/s source-series terminated I/O driver in a 65-nm CMOS process. The novel methodology is proposed to systematically analyze and predict the CM noise of an output driver from various dependent parameters, including CMOS process corners, input signal, power supply, and passive interconnections. Analysis reveals that the nonlinear active circuit predominantly produces an asymmetric rise and fall time of the output signal and is an intrinsic source responsible for generating the CM noise. For the SST driver, as the result of the push-pull nMOS-pMOS configuration, CM noise level variations are aggravated under process corners. The post-layout simulation results indicate that the critical step in controlling the CM noise is at the source, rather than improving the matching of passive interconnections. The presented methodology can also be applied to other serializer/deserializer I/O drivers.

This paper presents the design and study of a high performance microstrip rectangular patch antenna for the 2.5 GHz ISM band. The proposed antenna make use of small multiple circular slots embedded in the radiator to enhance the performance of the traditional patch antenna. Introduction of the new multi-slot arrangement offers a low profile antenna with reduced size, improved impedance matching, broadband operation. A comparatively wider -10 dB impedance bandwidth of 95 MHz is achieved. The maximum achievable gain is 6.8 dBi.Good performance, light weight, mechanically rugged and inexpensive design make this antenna a potential candidate for wireless portable devices.

This paper presents a CM noise suppression technique from self-calibration of a 20-Gb/s source-series terminated (SST) driver using an on-chip process monitoring circuit designed and simulated in a 65-nm CMOS process. An unbalanced charging and discharging loop results in an asymmetric rise and fall time of the output signal and is an intrinsic source of the CM noise. For an SST driver, the CM noise effect is especially aggravated under process corner variations due to push-pull NMOS configuration. The on-chip sensor circuit monitors and detects all possible process corners over the entire temperature range. The control circuit operates to self-calibrate the output driver to compensate for the process corner variations and results in a 15% higher symmetric rise and fall time of the output signal for the worst case scenario. The simulation results indicate that the proposed technique reduces the peak CM noise by 7.2x (-86%) without power overhead, as it is a background monitoring and self-calibration scheme.