Sensors provide data which need to be processed after acquisition to remove noise and extract relevant information. When the sensor is a network node and acquired data are to be transmitted to other nodes (e.g., through Ethernet), the amount of generated data from multiple nodes can overload the communication channel. The reduction of generated data implies the possibility of lower hardware requirements and less power consumption for the hardware devices. This work proposes a filtering algorithm (LDSI—Less Data Same Information) which reduces the generated data from event-based sensors without loss of relevant information. It is a bioinspired filter, i.e., event data are processed using a structure resembling biological neuronal information processing. The filter is fully configurable, from a “transparent mode” to a very restrictive mode. Based on an analysis of configuration parameters, three main configurations are given: weak, medium and restrictive. Using data from a DVS event camera, results for a similarity detection algorithm show that event data can be reduced up to 30% while maintaining the same similarity index when compared to unfiltered data. Data reduction can reach 85% with a penalty of 15% in similarity index compared to the original data. An object tracking algorithm was also used to compare results of the proposed filter with other existing filter. The LDSI filter provides less error (4.86 ± 1.87) when compared to the background activity filter (5.01 ± 1.93). The algorithm was tested under a PC using pre-recorded datasets, and its FPGA implementation was also carried out. A Xilinx Virtex6 FPGA received data from a 128 × 128 DVS camera, applied the LDSI algorithm, created a AER dataflow and sent the data to the PC for data analysis and visualization. The FPGA could run at 177 MHz clock speed with a low resource usage (671 LUT and 40 Block RAM for the whole system), showing real time operation capabilities and very low resource usage. The results show that, using an adequate filter parameter tuning, the relevant information from the scene is kept while fewer events are generated (i.e., fewer generated data).

Currently, there are some emerging online learning applications handling data streams in real-time. The On-line Sequential Extreme Learning Machine (OS-ELM) has been successfully used in real-time condition prediction applications because of its good generalization performance at an extreme learning speed, but the number of trainings by a second (training frequency) achieved in these continuous learning applications has to be further reduced. This paper proposes a performance-optimized implementation of the OS-ELM training algorithm when it is applied to real-time applications. In this case, the natural way of feeding the training of the neural network is one-by-one, i.e., training the neural network for each new incoming training input vector. Applying this restriction, the computational needs are drastically reduced. An FPGA-based implementation of the tailored OS-ELM algorithm is used to analyze, in a parameterized way, the level of optimization achieved. We observed that the tailored algorithm drastically reduces the number of clock cycles consumed for the training execution up to approximately the 1%. This performance enables high-speed sequential training ratios, such as 14 KHz of sequential training frequency for a 40 hidden neurons SLFN, or 180 Hz of sequential training frequency for a 500 hidden neurons SLFN. In practice, the proposed implementation computes the training almost 100 times faster, or more, than other applications in the bibliography. Besides, clock cycles follows a quadratic complexity $O\left({\tilde{N}}^2\right)$ , with $\tilde{N}$ the number of hidden neurons, and are poorly influenced by the number of input neurons. However, it shows a pronounced sensitivity to data type precision even facing small-size problems, which force to use double floating-point precision data types to avoid finite precision arithmetic effects. In addition, it has been found that distributed memory is the limiting resource and, thus, it can be stated that current FPGA devices can support OS-ELM-based on-chip learning of up to 500 hidden neurons. Concluding, the proposed hardware implementation of the OS-ELM offers great possibilities for on-chip learning in portable systems and real-time applications where frequent and fast training is required.

A rapid and accurate detection of ventricular arrhythmias is essential to take appropriate therapeutic actions when cardiac arrhythmias occur. Furthermore, the accurate discrimination between arrhythmias is also important, provided that the required shocking therapy would not be the same. In this work, the main novelty is the use of the mathematical method known as Topological Data Analysis (TDA) to generate new types of features which can contribute to the improvement of the detection and classification performance of cardiac arrhythmias such as Ventricular Fibrillation (VF) and Ventricular Tachycardia (VT). The electrocardiographic (ECG) signals used for this evaluation were obtained from the standard MIT-BIH and AHA databases. Two input data to the classify are evaluated: TDA features, and Persistence Diagram Image (PDI). Using the reduced TDA-obtained features, a high average accuracy near 99% was observed when discriminating four types of rhythms (98.68% to VF; 99.05% to VT; 98.76% to normal sinus; and 99.09% to Other rhythms) with specificity values higher than 97.16% in all cases. In addition, a higher accuracy of 99.51% was obtained when discriminating between shockable (VT/VF) and non-shockable rhythms (99.03% sensitivity and 99.67% specificity). These results show that the use of TDA-derived geometric features, combined in this case this the k-Nearest Neighbor (kNN) classifier, raises the classification performance above results in previous works. Considering that these results have been achieved without preselection of ECG episodes, it can be concluded that these features may be successfully introduced in Automated External Defibrillation (AED) and Implantable Cardioverter Defibrillation (ICD) therapies.

Due the fact that the required therapy to treat Ventricular Fibrillation ($VF$) is aggressive (electric shock), the lack of a proper detection and recovering therapy could cause serious injuries to the patient or trigger a ventricular fibrillation, or even death. This work describes the development of an automatic diagnostic system for the detection of the occurrence of $VF$ in real time by means of the time-frequency representation ($TFR$) image of the ECG. The main novelties are the use of the $TFR$ image as input for a classification process, as well as the use of combined classifiers. The feature extraction stage is eliminated and, together with the use of specialized binary classifiers, this method improves the results of the classification. To verify the validity of the method, four different classifiers in different combinations are used: Regression Logistic with L2 Regularization ($L2RLR$), adaptive neural network ($ANNC$), Bagging ($BAGG$), and K-nearest neighbor ($KNN$). The Hierarchical Method (HM) and Voting Majority Method (VMM) combinations are used. ECG signals used for evaluation were obtained from the standard MIT-BIH and AHA databases. When the classifiers were combined, it was observed that the combination of $BAGG$ , $KNN$ , and $ANNC$ using the Hierarchical Method (HM) gave the best results, with a sensitivity of 95.58 ± 0.41%, a 99.31 ± 0.08% specificity, a 98.6 ± 0.04% of overall accuracy, and a precision of 98.25 ± 0.29% for $VF$ . Whereas a sensitivity of 94.02 ± 0.58%, a specificity of 99.31 ± 0.08%, an overall accuracy of 99.14 ± 0.43%, and a precision of 98.59 ± 0.09% was obtained for $VT$ with a run time between 0.07 s and 0.12 s. Results show that the use of $TFR$ image data to feed the combined classifiers yields a reduction in execution time with performance values above to those obtained by individual classifiers. This is of special utility for $VF$ detection in real time.

Typically, hardware implemented neural networks are trained before implementation. Extreme learning machine (ELM) is a noniterative training method for single-layer feed-forward (SLFF) neural networks well suited for hardware implementation. It provides fixed-time learning and simplifies retraining of a neural network once implemented, which is very important in applications demanding on-chip training. This study proposes the data flow of a software support tool in the design process of a hardware implementation of on-chip ELM learning for SLFF neural networks. The software tool allows the user to obtain the optimal definition of functional and hardware parameters for any application, and enables the user to interact throughout the design process. Combining in a transparent way for the user, simulation and Xilinx synthesis tools, the tool recommends the optimal configuration, generating, finally, a synthesizable IP-core. As application, the field-programmable gate array implementation for real-time detection of brain areas in electrode positioning during a deep brain stimulation surgery is described. The generated IP-core can execute a peak of 95 ELM trainings per second on a low-cost Spartan 6 device, making possible its real-time use in this application.