Low thermal conductivity and large coefficient of thermal expansion (CTE) are the most serious disadvantages of the polymer dielectric for the interposer redistribution layer (RDL). In this paper, a high thermal conductivity and low CTE composite with polyimide (PI) matrix and diamond nanoparticles/SiC whiskers reinforcement is proposed. The preparation and characterization of the composite film are presented and the effects of the composite on the improvement of the interposer properties are investigated. With 10 wt% diamond-nanoparticles and 7 wt% SiC-whiskers, the composite film has a thermal conductivity of 1.63 W/m·K and a CTE of 16.7 ppm/°C (compared with 0.19 W/m·K and 55.6 ppm/°C of the PI). Interposers with PI RDL dielectric and the composite RDL dielectric are fabricated, respectively. The simulation result shows that the composite dielectric can significantly enhance the properties of the interposer compared with the PI dielectric. The thermal resistance of the interposer decreases from 8.04 °C/W to 1.15 °C/W. The maximum von Mises stress decreases from 72.8 MPa to 16.9 MPa and the warpage decreases from 1.13 μm to 0.15 μm. Thermal distribution tests are performed as well. The results show that the maximum temperature of the interposer decreases from 64 °C to 45.1 °C. The composite developed in this study can reduce the temperature and enhance the reliability of the chips with interposers. It has the potential to expand the application of the interposers in high thermal density integration and high reliability devices.

The application of a Si interposer is hindered by its complicated manufacturing process, high cost and some reliability challenges such as through silicon via (TSV) leakage. In this paper, a fabrication approach using a Si interposer is proposed, which can simplify the manufacturing process significantly and reduce the cost by more than 40%. Benefiting from the simplified process, the TSV insulation layer stays intact during the whole manufacturing process, an ultra-low TSV leakage current can be obtained. To evaluate the performance and reliability of the interposer, test samples consisting of 136 TSVs are designed and fabricated. A series of tests are carried out to verify the electrical insulating performance and reliability of the interposer. Under the bias voltage of 5 V, the TSV leakage current is 2.05 × 10 ⁻¹⁴ A, which is much lower than the usual value in the range of 10 ⁻¹² –10 ⁻⁹ A. The yield of daisy chains exceeds 91.66% and that of individual TSVs is more than 99.91%. All the interposer samples have successfully passed the thermal cycle test, and the resistance variation of each individual pathway is within 5% after 200 cycles.

A de-ionized water cooling system consisting of a microchannel heat sink and some equipment that can be applied to a chip is suggested. To optimize the structure, three kinds of pin fins (rhombus, pentagon and hexagon) are described. The heat transfer performance, the fluid flow and the pressure drop of the microchannel heat sink are simulated by commercial CFD solver Fluent. The inlet and the outlet are arranged at the side face of the heat sink. The volume of it is condensed, so other layer can be attached above or below to satisfy packaging. The maximum temperature of the chip with hexagon pin fins was the lowest one at a dissipation power of 50 W compared with other reference pin fin configurations.