This paper presents the key features of single photon avalanche diode (SPAD) devices fabricated in a low voltage commercial 180-nm CMOS image sensor technology exhibiting very low dark count rate (DCR). The measured DCR is <; 100 Hz at room temperature even for excess voltages above 2 V. The active junction of the SPAD measures 10 μm in diameter within a 24-μm test structure. The active region where Geiger avalanche occurs is determined by an implanted charge sheet. Edge avalanche is averted by utilizing a virtual guard ring, formed by the retrograde well profile. The design, measurements, and simulations of doping and electric field profiles that lead to such low DCR are reported and analyzed. The current-voltage characteristics and the temperature dependence of the breakdown voltage provide further, indirect evidence for the low DCR measured in the device. Thus, the key features of measured good SPADs are presented and are correlated with simulations that give physical insight on how to design high-performance SPADs.

This paper reports the design (electrical, mechanical, and thermal), fabrication technology by postcomplementary metal-oxide-semiconductor (CMOS) nanomachining, and characterization of CMOS-silicon on insulator (SOI)-nanoelectromechanical systems (NEMS) transistors fabricated in 180-nm technology. The thermally isolated, nanomachined CMOS-SOI-NEMS transistor reported here is designed for monolithic uncooled passive terahertz sensing and is dubbed “TeraMOS,” while the fabrication technology is dubbed "CMOST." With responsivity of ~0.5 A/W, noise equivalent power (NEP) of the order of NEP/√Hz|_{1 HZ} = 7.8 pW/√Hz, D* of 0.34 · 10¹⁰ cm√Hz/Watt, and evaluated noise equivalent temperature difference of ~1.25 K, this uncooled THz sensor in standard CMOS-SOI technology may enable monolithic uncooled passive THz imagers.

An approach useful for designing the passive quenching circuitry of single-photon avalanche diodes (SPADs) is presented. A method is introduced which enables a chip designer to correctly select the appropriate resistance of the passive quenching component of the chip. The range of external resistance required for adequate quenching can be determined solely from the measured dc I–V characteristics of the SPAD. The tradeoff between various allowable values of resistance is discussed.

A novel composite porous silicon/polysilicon microcantilever for biosensing applications with enhanced sensitivity is reported. It is fabricated by surface micromachining of polysilicon cantilevers followed by the formation of the surface porous layer after release by Reaction Induced Vapor Phase Stain Etch. The microcantilevers with porous surface layer are characterized by their morphology that exhibits a dual macro and nanostructure for very effective immobilization of biomolecules. The current work focuses on the fabrication of composite porous silicon/polysilicon microcantilevers, characterization of their morphology and resonance frequency, as well as demonstration of improved immobilization of enzyme resulting in enhanced sensing of triglycerides.