Realization of high-density and reliable resistive random access memories based on two-dimensional semiconductors is crucial toward their development in next-generation information storage and neuromorphic computing. Here, wafer-scale integration of solution-processed two-dimensional MoS₂ memristor arrays are reported. The MoS₂ memristors achieve excellent endurance, long memory retention, low device variations, and high analog on/off ratio with linear conductance update characteristics. The two-dimensional nanosheets appear to enable a unique way to modulate switching characteristics through the inter-flake sulfur vacancies diffusion, which can be controlled by the flake size distribution. Furthermore, the MNIST handwritten digits recognition shows that the MoS₂ memristors can operate with a high accuracy of >98.02%, which demonstrates its feasibility for future analog memory applications. Finally, a monolithic three-dimensional memory cube has been demonstrated by stacking the two-dimensional MoS₂ layers, paving the way for the implementation of two memristor into high-density neuromorphic computing system.

Realization of memristors capable of storing and processing data on flexible substrates is a key enabling technology toward “system‐on‐plastics”. Recent advancements in printing techniques show enormous potential to overcome the major challenges of the current manufacturing processes that require high temperature and planar topography, which may radically change the system integration approach on flexible substrates. However, fully printed memristors are yet to be successfully demonstrated due to the lack of a robust printable switching medium and a reliable printing process. An aerosol‐jet‐printed Ag/MoS₂/Ag memristor is realized in a cross‐bar structure by developing a scalable and low temperature printing technique utilizing a functional molybdenum disulfide (MoS₂) ink platform. The fully printed devices exhibit an ultra‐low switching voltage (0.18 V), a high switching ratio (10⁷), a wide range of tuneable resistance states (10–10¹⁰ Ω) for multi‐bit data storage, and a low standby power consumption of 1 fW and a switching energy of 4.5 fJ per transition set. Moreover, the MoS₂ memristor exhibits both volatile and non‐volatile resistive switching behavior by controlling the current compliance levels, which efficiently mimic the short‐term and long‐term plasticity of biological synapses, demonstrating its potential to enable energy‐efficient artificial neuromorphic computing.

3D monolithic integration of logic and memory has been the most sought after solution to surpass the Von Neumann bottleneck, for which a low-temperature processed material system becomes inevitable. Two-dimensional materials, with their excellent electrical properties and low thermal budget are potential candidates. Here, we demonstrate a low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe₂p-FET, with a solution-processed WSe₂ Resistive Random Access Memory. The employed plasma oxidation technique results in a low Schottky barrier height of 25 meV with a mobility of 230 cm² V⁻¹ s⁻¹, leading to a 100x performance enhanced WSe₂p-FET, while the defective WSe₂ Resistive Random Access Memory exhibits a switching energy of 2.6 pJ per bit. Furthermore, guided by our device-circuit modelling, we propose vertically stacked channel FETs for high-density sub-0.01 μm² memory cells, offering a new beyond-Si solution to enable 3-D embedded memories for future computing systems.

Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNFETs vs. advanced technology options (ATOs) currently under consideration (e.g., silicon-germanium (SiGe) channels and progressing from today's FinFETs to gate-all-around nanowires/nanosheets). We use industry-practice physical designs of digital VLSI processor cores in future technology nodes with millions of transistors (including effects from parasitics and interconnect wires) and technology parameters extracted from experimental data. Our analysis shows that CNFETs are projected to offer 9× energy-delay product (EDP) benefit (~3× faster while simultaneously consuming ~3× less energy) compared to Si/SiGe FinFET. The ATOs provide $\lt50\%$ EDP benefits. All analyses are performed at the same off-state leakage current density ( $\le100$ nA per micron of FET width) and power density ( $\le100$ Watts per $\rm cm^2$ of chip area). This analysis provides insights into the sources of CNFET EDP benefits and addresses key questions for deeply-scaled technologies. For instance, while contact resistance is a concern for sub-10 nm nodes, CNFETs still provide up to (6.0×) EDP benefit (vs. Si/SiGe FinFETs) using CNFET contact resistance values already experimentally achieved for 9 nm contact length

Photonic neural network has been sought as an alternative solution to surpass the efficiency and speed bottlenecks of electronic neural network. Despite that the integrated Mach–Zehnder Interferometer (MZI) mesh can perform vector-matrix multiplication in photonic neural network, a programmable in-situ nonlinear activation function has not been proposed to date, suppressing further advancement of photonic neural network. Here, we demonstrate an efficient in-situ nonlinear accelerator comprising a unique solution-processed two-dimensional (2D) MoS₂ Opto-Resistive RAM Switch (ORS), which exhibits tunable nonlinear resistance switching that allow us to introduce nonlinearity to the photonic neuron which overcomes the linear voltage-power relationship of typical photonic components. Our reconfigurable scheme enables implementation of a wide variety of nonlinear responses. Furthermore, we confirm its feasibility and capability for MNIST handwritten digit recognition, achieving a high accuracy of 91.6%. Our accelerator constitutes a major step towards the realization of in-situ photonic neural network and pave the way for the integration of photonic integrated circuits (PIC).