This paper introduces a unified approach to the validation of power-electronics (PE) control hardware, firmware, and software designs. It is based on a scalable application-specific ultralow-latency (ULL) digital processor core. The proposed ULL processor core simulates PE converters and systems comprising multiple power converters with a fixed 1-μs simulation time step and latency, regardless of the size of the system. Owing to its ULL, the proposed platform enables the fully automatic testing and validation of the complete PE design comprising component safe-operating-area validation, system protection, firmware, and software implementation as well as overall system performance optimization.

The aim of this paper is to present a universal power quality conditioning system (UPQS) named after unified power quality conditioner, which is extended by adding a shunt active filter at the load side. Its main purpose is to compensate for both supply voltage and load current imperfections, such as: sags, swells, interruptions, imbalance, flicker, harmonics, reactive currents and current unbalance. Such system has better harmonic compensation characteristic, since there are no problems associated with passive filter operation. Converter and control analysis is presented, together with results showing the UPQS modes of operation

This paper proposes two power flow control algorithms for a grid-connected voltage source converter used as part of the energy storage for a smart grid under unbalanced voltage conditions. Both algorithms are improvements of the dual vector current control algorithm (DVCC). The first proposed algorithm, DVCC_CL, optimizes the method of limiting phase currents for the duration of voltage unbalance. The second proposed algorithm, DVCC_HB, provides high bandwidth control of active and reactive power. Which of the two proposed algorithms is the better choice depends on the grid code requirements and the constraints imposed by the particular energy storage system which the inverter connects to the grid. The operation of both algorithms was verified within the framework of an ultralow-latency hardware-in-the-loop emulator, which makes accurate analysis of converter behavior safe and easy for any grid conditions.

This paper proposes an energy conversion system for a wind turbine comprising a grid connected permanent magnet synchronous generator and a 20% rated series converter located in its star point. It models the complete system and focuses on the series converter control whose primary function is the active damping of the generator. In addition, this paper addresses the topic of the dc bus voltage control and the dc capacitance sizing of the series converter. Finally, it validates the performance of the proposed system by means of system simulation.

Prototyping and verification of complex power electronics (PE) systems and control algorithms is a laborious and time-consuming process. Even when a low-power hardware model is assembled, it enables only a limited insight into the large number of operating points; changes in system parameters regularly demand hardware modifications and always there is the risk of hardware damage. The ultralow-latency Hardware-In-the-Loop (HIL) platform proposed in this paper combines the flexibility, accuracy, and ease of use of state-of-the-art-simulation packages, with the response speed of small power-hardware models. In this way, PE systems-optimization, code-development, and laboratory-testing can be combined into one step, which dramatically accelerates the pace of product prototyping. Low-power hardware-models also suffer from nonscalability, because some parameters such as electrical machine inertia cannot be properly scaled. However, HIL enables control prototyping that covers all operational conditions. In order to demonstrate HIL-based rapid development, the verification of an active damping algorithm for a permanent magnet synchronous generator (PMSG) cascade is performed. Two goals are set in this paper: to verify the developed HIL platform by means of comparison with a low-power hardware setup and then to emulate the real, high-power system in order to test the active damping algorithm.