In the Bitcoin network, computing double SHA-256 values consumes most of the network energy. Therefore, reducing the power consumption and increasing the processing rate for the double SHA-256 algorithm is currently an important research trend. In this paper, we propose a high-data-rate low-power hardware architecture named the compact message expander (CME) double SHA-256. The CME double SHA-256 architecture combines resource sharing and fully unrolled datapath technologies to achieve both a high data rate and low power consumption. Notably, the CME algorithm utilizes the double SHA-256 input data characteristics to further reduce the hardware cost and power consumption. A review of the literature shows that the CME algorithm eliminates at least 9.68% of the 32-bit XOR gates, 16.49% of the 32-bit adders, and 16.79% of the registers required to calculate double SHA-256. We synthesized and laid out the CME double SHA-256 using CMOS 0.18 μm technology. The hardware cost of the synthesized circuit is approximately 13.88% less than that of the conventional approach. The chip layout size is 5:9mm×9mm, and the correctness of the circuit was verified on a real hardware platform (ZCU 102). The throughput of the proposed architecture is 61.44 Gbps on an ASIC with Rohm 180nm CMOS standard cell library and 340 Gbps on a FinFET FPGA 16nm Zynq UltraScale+ MPSoC ZCU102.

The development of a low-cost high-performance secure hash algorithm (SHA)-256 accelerator has recently received extensive interest because SHA-256 is important in widespread applications, such as cryptocurrencies, data security, data integrity, and digital signatures. Unfortunately, most current researches have focused on the performance of the SHA-256 accelerator but not on a system level, in which the data transfer between the external memory and accelerator occupies a large time fraction. In this paper, we solve the state-of-art problem with a novel SHA-256 architecture named the multimem SHA-256 accelerator that achieves high performance at the system on chip (SoC) level. Notably, our accelerator employs three novel techniques, the pipelined arithmetic logic unit (ALU), multimem processing element (PE), and shift buffer in shift buffer out (SBi-SBo), to reduce the critical path delay and significantly increase the processing rate. Experiments on a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) show that the proposed accelerator achieves significantly better processing rate and hardware efficiency than previous works. The accelerator accuracy is verified on a real hardware platform (FPGA ZCU102). The accelerator is synthesized and laid out with 180 nm complementary metal oxide semiconductor (CMOS) technology with a chip sized $8.5\,mm \times 8.5\,mm$ , consumes 1.86 W, and provides a maximum processing rate of 40.96 Gbps at 80 MHz and 1.8 V. With FPGA Xilinx 16 nm FinFET technology, the accelerator processing rate is as high as 284 Gbps.

The secure hash algorithm 2 (SHA-2) family, including the SHA-224/256/384/512 hash functions, is widely adopted in many modern domains, ranging from Internet of Things devices to cryptocurrency. SHA-2 functions are often implemented on hardware to optimize performance and power. In addition to the high-performance and low-cost requirements, the hardware for SHA-2 must be highly flexible for many applications. This paper proposes an SHA-2 hardware architecture named the multimode SHA-2 accelerator (MSA), which has high performance and flexibility at the system-on-chip level. To achieve high performance and flexibility, our accelerator applies three optimal techniques. First, a multimode processing element architecture is proposed to enable the accelerator to compute various SHA-2 functions for many applications. Second, a three-stage arithmetic logic unit pipeline architecture is proposed to reduce the critical paths and hardware resources. Finally, nonce generator and nonce validator architectures are proposed to reduce memory access and maximize the performance of the proposed MSA for blockchain mining applications. The MSA accuracy is tested on a real hardware platform (the Xilinx Alveo U280 FPGA). The experimental results on the field programmable gate array (FPGA) prove that the proposed MSA achieves significantly better performance, hardware efficiency, and flexibility than previous works. The evaluation results for energy efficiency show that the proposed MSA achieves up to 38.05 Mhps/W, which is 543.6 and 29 times better than the state-of-the-art Intel i9-10940X CPU and RTX 3090 GPU, respectively.

Blockchain distributed ledger technology (DLT) has widespread applications in society 5.0 because it improves service efficiency and significantly reduces labor costs. However, employing blockchain DLT entails considerable energy consumption in the mining process. This paper proposes a blockchain accelerator (BCA) with ultralow power consumption and a high processing rate to address the problem. The BCA focuses on accelerating the double secure hash algorithm (SHA) 256 function required in the mining process at a system-on-chip (SoC) level. We propose three ideas, namely, multiple local memories (multimem), double-cell processing element (D-PE), and nonce autoupdate (NAU), to reduce the external data transfer time and improve the BCA hardware efficiency. We propose a cascaded multiple BCA chip model to enhance the system throughput by several-fold. Our experiments on an ASIC and FPGA prove that the proposed BCA successfully performs the mining process for multiple blockchain networks with much lower power consumption than that of the state-of-the-art CPUs and GPUs. The BCA is laid out with Renesas 65 nm technology with a chip area of $25~mm^{2}$ and consumes $530~mW$ at 100 MHz . The power efficiency of the layout chip is improved by 2428 and 143 times compared with that of the fastest CPU Intel i9-10940X and GPU RTX 3090, respectively.

Classification is a crucial aspect of cardiovascular-related challenges, requiring thorough research and optimization to develop effective solutions for both patients and doctors. Recently, rapid advancements in artificial intelligence, particularly Convolutional Neural Networks (CNNs), have introduced numerous effective methods, significantly improving disease classification in Electrocardiogram (ECG) analysis. However, existing CNN-based accelerators often encounter challenges such as high parameter counts, limited flexibility in handling diverse CNN configurations, and inefficient hardware utilization. To address these issues, this paper proposes the Mini InceptionNet Accelerator (MINA), a hardware-efficient and flexible accelerator designed specifically for one-dimensional (1-D) CNN-based ECG classification. First, a novel 1-D CNN model, Mini InceptionNet, reduces the parameter count by 41.6% compared to the smallest existing 1-D CNN, minimizing memory requirements while maintaining high classification accuracy. Second, a flexible Processing Element Array (PEA) is designed with a Sharing Buffer Allocator (SBA) to support dynamic data coordination across various network topology parameters. Third, each Processing Element (PE) is equipped with four Local Data Memories (LDMs) and an ALU, enabling efficient intermediate data storage and versatile operations for modern CNN models. To demonstrate its effectiveness, MINA has been successfully implemented and verified on the ZCU102 FPGA at the system-on-chip level. FPGA evaluations show that MINA achieves $1.3\times - 2.9\times $ higher energy efficiency (GOP/s/MeLUT) than state-of-the-art 2-D CNN accelerators. Compared to existing 1-D CNN accelerators, MINA achieves at least $1.53\times $ improvement in the area-delay product (ADP). Additionally, weight pruning is discussed as a supporting strategy, achieving up to $3\times $ faster inference time and a $2.13\times $ improvement in ADP at 70% sparsity.

Emerging modern internet-of-things (IoT) systems require hardware development to support multiple 8/32/64-bit lightweight cryptographic (LWC) algorithms with high speed and energy efficiency to ensure diverse security requirements. Accordingly, a coarse-grained reconfigurable array (CGRA) is considered the most effective architecture for achieving high speed, low power, and high flexibility for implementing LWC algorithms. However, existing CGRA designs for cryptography focus only on improvements to outdated 8/32-bit algorithms, suffer from large area requirements, and have long compilation times. To address these issues, this paper proposes a new CGRA-based accelerator named LiCryptor to support various 8/32/64-bit LWC algorithms with high speed and small area. Three innovative ideas are proposed to enable LiCryptor to achieve these goals: a compact multi-grained processing element array (M-PEA), a shared 8/32/64-bit arithmetic logic unit (ALU), and an assembly-like inline directive (AID) mapping method. The LiCryptor has been successfully implemented and verified on the Xilinx ZCU102 FPGA. Real-time performance evaluation across various LWC algorithms on FPGA shows that LiCryptor is 1.33 to 4 times better in execution time and 3.4 to 153 times better in power-delay products (PDP) compared to today’s most powerful CPUs. Notably, evaluation of AID mapping on the ARM Cortex-A53 CPU of the ZCU102 FPGA shows that its compilation time is less than 1.5 ms for most LWC algorithms, at least 2,333 times faster than CFG mapping in current CGRAs. Moreover, experimental results on 45nm ASIC technology show that the LiCryptor significantly outperforms existing CGRAs and other reconfigurable designs in terms of throughput and area efficiency.