This paper proposes a high power-performance-area efficient background noise aware keyword-spotting (KWS) processor based on an optimized binarized weight network (BWN). To reduce the power consumption while maintaining the system recognition accuracy for different background noise, the KWS processor with a SNR prediction module can be adaptively configured to use dual computing modes (standard computing mode and approximate computing mode) for both high recognition accuracy under high background noise and ultra-low power consumption under low background noise. The mel-scale frequency cepstral coefficients (MFCC) module is optimized with approximate computing technologies, which can reduce the power consumption by up to 3.1x and 5.7x for high/low background noise, respectively. Based on the evaluation of the architecture design space exploration, an ultra-low power BWN accelerator with low voltage, area and leakage power and using precision self-adaptive approximate computing units was proposed. Evaluated under 22nm process technology, this work can support up to 10 keywords real time recognition with power consumption of 15.1μW for high background noise and 10.8μW for low background noise. Compared to the state-of-the-art KWS architectures, our work can achieve ultra-low power consumption (about 1.7x reduced), while maintaining high system capability and adaptability.

In-memory computing (IMC) is an effective solution for energy-efficient artificial intelligence applications. Analog IMC amortizes the power consumption of multiple sensing amplifiers with an analog-to-digital converter (ADC) and simultaneously completes the calculation of multi-line data with a high parallelism degree. Based on a universal one-transistor one-magnetic tunnel junction (MTJ) spin transfer torque magnetic RAM (STT-MRAM) cell, this paper demonstrates a novel tunneling magnetoresistance (TMR) ratio magnifying method to realize analog IMC. Previous concerns including low TMR ratio and analog calculation nonlinearity are addressed using device-circuit interaction. The TMR is magnified $7500\times $ using a latch structure in combination with the device. Peripheral circuits are minimally modified to enable in-memory matrix-vector multiplication. A current mirror with a feedback structure is implemented to enhance analog computing linearity and calculation accuracy. The proposed design maximumly supports 1024 2-bit input and 1-bit weight multiply-and-accumulate (MAC) computations simultaneously. The proposal is simulated using the 28-nm CMOS process and MTJ compact model. The integral nonlinearity is reduced by 57.6% compared with the conventional structure. 9.47-25.4 TOPS/W is realized with 2-bit input, 1-bit weight, and 4-bit output convolution neural network (CNN).

In Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM), the most commonly used timing scheme for conventional Voltage-mode Sense Amplifier (VSA) is the global activated timing. Obviously this method cannot obtain the optimal yield because different bit-cells have its sensing latency respectively. This paper proposes a self-timed voltage-mode sense scheme named ST-VSS which can enable optimal timing depending on the bit-cell discharging ability. Two circuit structures are proposed: The single SA structure uses a multiplexer at the input of the SA. Its successive sensing operations are implemented with input offset flipping. A dual SA structure is reconfigured by built-in-self-test (BIST) method to the opposite offset states to monitor sensing results from each other. The sensing operation can be immediately terminated after successful reading. The proposed ST-VSS is applied to a 32bits/word MRAM using 28-nm CMOS process. Simulation results show that the successful sensing rate across a wide range of voltages can be improved, comparing with the conventional scheme. The single SA structure obtains 32%~42% yield improvement, costs 44.1%/26.9%/19.3% energy, and brings 8.3%/5.8%/2.9% layout area penalty in 128/256/512 column depth, respectively. The dual SA structure gets 54%~65% yield improvement, costs 66.2%/38.6%/27.5% energy, and brings 26.4%/13.8%/7.1% area penalty in 128/256/512 column depth conditions, respectively.

This paper proposes a hybrid deep neural network (DNN) for automatic speech recognition and an energy-efficient reconfigurable architecture with approximate computing for accelerating the DNN. To accelerate the hybrid DNN and reduce the energy consumption, we propose a digital–analog mixed reconfigurable architecture with approximate computing units, including a binary weight network accelerator with analog multi-chain delay-addition units for bit-wise approximate computing and a recurrent neural network accelerator with approximate multiplication units for different calculation accuracy requirements. Implemented under TSMC 28nm HPC+ process technology, the proposed architecture can achieve the energy efficiency of 163.8TOPS/W for 20 keywords recognition and 3.3TOPS/W for common speech recognition.