This paper designs a Low Noise Amplifier (LNA) used in RF front end receiver system for wireless sensor network applications. The proposed LNA adopt post distortion technique. This Low Noise Amplifier provides a low noise figure of 2.14dB with a forward gain of 16.6dB. The LNA circuit consumes a power of 11.6mW for 1.8V supply. The circuit is implemented using 180nm CMOS technology.

Convolution plays major role in deep learning. CNN is the basic architecture and most of the other deep learning architectures ae built based on CNN. However, 1D-CNN is suitable for EEG signals as it is time-series one dimensional characteristic signal. In this paper, we have proposed a 6-layer 1D-CNN to analyze the classification of EEG. Elliptic filter helps to filter Multivariate EEG signal of sleep apnea patient and then classify sleep stages using CNN. Simulations are carried out using Mat Lab.

Purpose: The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V. Design/methodology/approach: In this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates. Findings: The proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. Originality/value: In arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.

The privacy of patients can be influenced by counters used in health care systems. By properly placing the counters in queue far from the staff-patient communication cabin the privacy of individual health information can be protected from getting disclosed to other patients. The number of counters required in software defined radio to collect global information is very high. The implementation of many counters using ASIC is a challenging task in terms of accuracy, control flexibility and memory consumption. In this paper, we have designed 16 bit counter using cadence tool in 180nm technology. Floor planning for the counter is done and simulated by number of iterations to decrease the glitch violations to zero. By this method the counter gets offload management and updates to any software thereby executes efficiently in hardware practically.