An inserted novel polarization-graded AlGaN back barrier structure is designed to enhance performances of In_0.17Al_0.83N/GaN high electron mobility transistor (HEMT), which is investigated by the two-dimensional drift-diffusion simulations. The results indicate that carrier confinement of the graded AlGaN back-barrier HEMT is significantly improved due to the conduction band discontinuity of about 0.46 eV at interface of GaN/AlGaN heterojunction. Meanwhile, the two-dimensional electron gas (2DEG) concentration of parasitic electron channel can be reduced by a gradient Al composition that leads to the complete lattice relaxation without piezoelectric polarization, which is compared with the conventional Al_0.1Ga_0.9N back-barrier HEMT. Furthermore, compared to the conventional back-barrier HEMT with a fixed Al-content, a higher transconductance, a higher current and a better radio-frequency performance can be created by a graded AlGaN back barrier.

This paper presents a high quality-factor (Q) and spectrum-clean AlN Lamb-wave resonator (LWR). The width of its lateral reflection boundary was optimized to weaken the transverse modes’ coupling and wave guiding, and then to improve the LWR’s Q value and spectral purity, which was verified by finite element analysis and experimental characterization. In addition, the series resonance quality factor (Q_s) value of the interdigitated (IDT)-Ground LWR is similar to that of the IDT-Floating LWR, but its parallel resonance quality factor (Q_p) is nearly doubled, due to the reduction of the electrical loss induced by its static capacitance (C₀). The measured results show that the designed LWR with optimized boundary reflection conditions and IDT-Ground structure exhibit Q_s and Q_p values as high as 4019.8 and 839.5 at 401.2 MHz and 402.9 MHz, respectively, meanwhile, it has good spectral purity. Moreover, the influence of the metal ratio and material of the LWR’s IDT electrodes on the device’s performance was also studied by theoretical analysis and experimental verification.

A chiplet multi-objective optimization algorithm for 2.5-D integrated circuit (IC) based on a passive interposer is discussed in this article. Inspired by the network-on-chip mapping problem, we propose a novel algorithm, called chiplet multi-objective optimization, which minimizes the average temperature and the communication consumption between chiplets at the same time. The algorithm considers the specificities of 2.5-D IC chiplets, such as the spacing and different sizes of chiplets. In addition to the weight factor, α is also introduced to make a balance between temperature and the communication consumption. The designer can change the weight factor according to their own requirement. The multi-window display system is used as an example in this article to demonstrate the algorithm’s efficiency and the accuracy. According to our algorithm, the system temperature of the most ideal solution can be reduced by 8.34 K and the communication consumption reduced by 232.13 μJ.

This paper presents a micro-electro-mechanical systems (MEMS) processing technology for Aluminum Nitride (AlN) Lamb-wave resonators (LWRs). Two LWRs with different frequencies of 402.1 MHz and 2.097 GHz by varying the top interdigitated (IDT) periods were designed and fabricated. To avoid the shortcomings of the uncontrollable etching of inactive areas during the releasing process and to improve the fabrication yield, a thermal oxide layer was employed below the platted polysilicon sacrificial layer, which could define the miniaturized release cavities well. In addition, the bottom Mo electrode that was manufactured had a gentle inclination angle, which could contribute to the growth of the high-quality AlN piezoelectric layer above the Mo layer and effectively prevent the device from breaking. The measured results show that the IDT-floating resonators with 12 μm and 2 μm electrode periods exhibit a motional quality factor (Q_m) as high as 4382 and 1633. The series resonant frequency (f_s)·Q_m values can reach as high as 1.76 × 10¹² and 3.42 × 10¹², respectively. Furthermore, Al is more suitable as the top IDT material of the AlN LWRs than Au, and can contribute to achieving an excellent electrical performances due to the smaller density, smaller thermo-elastic damping (TED), and larger acoustic impedance difference between Al and AlN.

This work presents a laterally excited bulk wave resonator (XBAR) based on the suspended Z-cut lithium niobate thin film. In order to systematically analyze the influence of geometric structure on the performance of resonators, including electromechanical coupling coefficient (k_t ²) and quality factor (Q), the pitch of inter-digital transducers and lateral reflective boundary width (D) were optimized via finite element analysis simulation. Besides, the XBARs with the broadband piston mode structure (BPM-XBAR) were further studied, and the transverse displacement was weakened after optimization, hence enhancing the Q value of the targeted mode. Consequently, the fabricated devices exhibited first order asymmetrical (A1) mode resonance at 5.87 GHz with k_t ² of 12.98% and Q of 218, a nearly 70% increase in Q value. The third order asymmetrical (A3) mode resonance occurred at 17.18 GHz with k_t ² of 7.91%. The above devices have the potential to construct large bandwidth and low loss filters toward the C-band and Ku-band.

A chiplet placement algorithm for 2.5-D IC integration on an interposer is discussed in this paper. Inspired by the NoC (network-on-chip) mapping problem, we propose a novel chiplet placement algorithm called the CCEOA (chiplet communication energy optimization algorithm), which takes into account the actual size of the chiplet. The CCEOA can map chiplets to mesh topology, resulting in a layout with a low CEC (communication energy consumption). The algorithm considers the spacing of the chiplets while selecting the initial nodes and the nodes to map the next chiplet. Furthermore, because there exist nodes resulting in the same CEC increment during the mapping process, the algorithm adopts a secondary local exploration strategy to further select nodes. Meanwhile, the lateral and vertical placements of chiplets are also considered. The algorithm is implemented and evaluated with a 2.5-D IC integration with 22 chiplets to demonstrate its efficiency and the accuracy.