This paper presents a new analog circuit optimization system for automated sizing of analog integrated circuits. It consists of a genetic algorithm (GA)-based global optimization engine and an artificial neural network (ANN)-based local optimization engine. The key new idea is to use parallel computation to train ANN models for design space neighborhoods thus the local minimum search (LMS) can have a much faster search speed. For the GA-based global optimization, circuit performances are calculated by parallel SPICE simulations. For the LMS, circuit performance data are derived from ANN model predictions instead of SPICE simulations. Since most time for an ANN-based LMS is spent on SPICE calls which can be run in parallel, the LMS process can also exploit the multiple core configuration of a modern computational server in addition to the GA global search. The fully parallelized optimization system is deployed to design a two-stage rail-to-rail operational amplifier and a 5th-order active-RC Chebyshev complex band-pass filter. Experimental results show that the proposed method provides about four times speed enhancement and comparable results compared with traditional approaches employing the same parallel global optimization but sequential SPICE calls during LMS.

The developing optimization algorithms provide promising solutions for speeding up analog integrated circuit sizing. However, the optimization of complicated circuits whose solution regions are narrow remains to be a challenge. With a limited number of sampling points due to the restriction of computational resources, it is difficult for traditional algorithms to achieve satisfactory results for such circuits. To solve this problem, this article proposes a rule-guided genetic algorithm (RG-GA) for analog circuit optimization. Different from the random mutation approach in the traditional genetic algorithm (GA), the RG-GA introduces a design rule-guided mutation (RGM) mechanism which helps to find the solution region in a more straightforward fashion. Instead of handing over circuit optimization tasks to pure mathematical algorithms, the proposed method takes advantages of valuable design knowledge to improve searching efficiency. This novel algorithm is implemented and deployed to design a two-stage rail-to-rail operational amplifier (OPA), an LC voltage controlled oscillator (LC-VCO) and a four-stage OPA. Experimental results show that compared to the traditional GA method, the RG-GA achieves about 1.5 and 3.3 times speed enhancement for the two-stage rail-to-rail OPA and the LC-VCO, respectively. For the four-stage OPA, the RG-GA method can find an acceptable point within the given number of iterations while the traditional GA could not.

Binarized convolutional neural networks (bCNNs) are favored for the design of low-storage, low-power cardiac arrhythmia classifiers owing to their high weight compression rate. However, multi-class classification of ECG signals based on bCNNs is challenging due to the accuracy loss introduced by the binarization operation. In this paper, an effective multi-classifier system is proposed for electrocardiogram (ECG) signals using a binarized depthwise separable convolutional neural network (bDSCNN) with the merged convolution–pooling (MCP) method. The binarized depthwise separable convolution layer is adopted to reduce the increased number of parameters in multi-classification systems. Instead of operating convolution and pooling sequentially as in a traditional convolutional neural network (CNN), the MCP method merges pooling together with convolution layers to reduce the number of computations. To further reduce hardware resources, this work employs blockwise incremental calculation to eliminate redundant storage with computations. In addition, the R peak interval data are integrated with P-QRS-T features to improve the classification accuracy. The proposed bDSCNN model is evaluated on an Intel DE1-SoC field-programmable gate array (FPGA), and the experimental results demonstrate that the proposed system achieves a five-class classification accuracy of 96.61% and a macro-F1 score of 89.08%, along with a dynamic power dissipation of 20 μW for five-category ECG signal classification. The hardware resource usage of BRAM and LUTs plus REGs is reduced by at least 2.94 and 1.74 times, respectively, compared with existing ECG classifiers using bCNN methods.

This paper presents a fully integrated CMOS radio-frequency (RF) transceiver for BeiDou-1, a radio determination satellite service system which can provide regional positioning and short message service. The proposed transceiver incorporates a low-IF receiver and a BPSK transmitter to realize a dual-way communication between users and the central control station via satellites. The receiver (RX) RF front-end down-converts the 2491.75 MHz RF signals to a 12.24 MHz IF band with a bandwidth of 8.16 MHz. The complex band-pass filter utilizes passive compensation technique to compensate the phase lag and achieve in-band flatness. The 4.08 Mchip/s baseband signal alternatively selects one of the differential 1615.68 MHz local signals to achieve BPSK modulation for the transmitter (TX). Besides, on-chip low dropout regulators adopt improved power supply rejection ratio techniques by integrating active filtering to obtain stable 1.5 V supply voltages. The transceiver is fabricated in a 130 nm CMOS technology and occupies an area of 5.88 mm2 with electrostatic discharge circuitry and pads included. The RX channel achieves a 106 dB maximum voltage gain with a 65 dB dynamic range, a 4.95 dB noise figure and a 46 dB image rejection ratio. The output power for the TX ranges from -10 dBm to 5 dBm, with a phase error less than 1.5 degree.

With the scaling down of the transistor technology, intrinsic gains of the devices are continuously dropping. Meanwhile, high-gain operational transconductance amplifiers (OTAs) using technologies with reduced feature sizes are required in various applications. This article presents a 55-nm-fabricated three-stage OTA with a single cascode Miller capacitor for driving large capacitive loads. To achieve a high dc gain, a gain enhancement (GE) circuit is used in the first stage to boost the overall voltage gain to above 100 dB. To obtain a stable frequency response, a cascode Miller compensation scheme together with the GE circuits are used to push the nondominant complex pole to higher frequency and adjust the $Q$ -factor. The proposed three-stage OTA is implemented in a 55-nm low-power (LP) CMOS process and occupies an area of 0.005 mm $^2$ . A current consumption of 157 $\mu$ A can be measured with a supply voltage of 1.2 V. The measured results show that this three-stage OTA can achieve stable frequency and transient step responses when driving 2.5-to-30-nF capacitive loads. With a 15-nF capacitive load, a gain bandwidth (GBW) of 0.82 MHz, a phase margin (PM) of 53 $^\circ$ , an average slew rate of 0.13 V/ $\mu$ s, and an average 1% settling time of 2.62 $\mu$ s can be achieved.

A low-power wireless acoustic sensing platform for remote surveillance applications based on a 180 nm CMOS technology is proposed in this paper. The audio signal, which is acquired by a microphone, is first amplified and filtered. Then, the analog signal is converted to a digital signal by a 10-bit analog-to-digital converter (ADC). A digital automatic gain control module is integrated to obtain an optimal input of the ADC. The digital signal is modulated and transmitted at the 433 MHz ISM band after being repacked and encoded. To save power for portable applications, the chip switches to standby mode when no audio is detected. The wireless sensing platform occupies a chip area of 1.76 mm ${}^2$ . The supply voltage is 2.5 V for the power amplifier and 1.8 V for other circuits. The measured maximum output power is 5.7 dBm and the transmission distance is over 500 m for real application scenarios. The chip consumes 25.1 mW power in normal work mode and 0.058 mW in standby mode. Compared to existing wireless acoustic sensors, the proposed wireless acoustic sensing platform can achieve features such as compactness, power efficiency, and reliability.