Measuring techniques of the die surface temperature in integrated circuits are reported as very appropriate for failure analysis, for thermal characterization, and for testing modern devices. The paper is arranged as a survey of techniques oriented towards measuring the temperature dynamics of the circuit surface and presenting and discussing both the merits and drawbacks of each technique with regard to the accuracy, reliability and efficiency of the measurements. Two methods are presented in detail: laser probing methods, based on interferometry and thermoreflectance, and embedded CMOS circuit sensors. For these techniques, the physical principles, the state of the art in figures of merit and some application examples are presented

The power dissipated by the devices of a circuit can be construed as a signature of the circuit's performance and state. Without disturbing the circuit operation, this power consumption can be monitored by temperature measurements of the silicon die surface via built-in differential temperature sensors. In this paper, dynamic and spatial thermal behavioral characterization of VLSI MOS devices is presented using laser thermoreflectance measurements and on-chip differential temperature sensing circuits. A discussion of the application of built-in differential temperature measurements as an IC test strategy is also presented.

We present a built-in, defect-oriented test approach for RF circuits that is based on thermal monitoring. A defect will change the power dissipation of the circuit under test from its expected range of values which, in turn, will induce a change in the expected temperature in the substrate near the circuit. Thus, an on-chip temperature sensor that monitors the temperature near the circuit can reveal the existence of the defect. This test approach has the key advantage of being non-intrusive and transparent to the design since the temperature sensor is not electrically connected to the circuit. We discuss the basics of thermal monitoring, the design of the temperature sensor, as well as the test scheme. The technique is demonstrated on fabricated chips where a temperature sensor is employed to monitor an RF low noise amplifier.

The focus in this paper is on the extraction of RF circuit performance characteristics from the dc output of an on-chip temperature sensor. Any RF input signal can be applied to excite the circuit under examination because only dissipated power levels are measured, which makes this approach attractive for online thermal monitoring and built-in test scenarios. A fully differential sensor topology is introduced that has been specifically designed for the proposed method by constructing it with a wide dynamic range, programmable sensitivity to dc, and RF power dissipation, as well as compatibility with CMOS technology. This paper also presents an outline of a procedure to model the local electrothermal coupling between heat sources and the sensor, which is used to define the temperature sensor's specifications as well as to predict the thermal signature of the circuit under test. A prototype chip with an RF amplifier and temperature sensor was fabricated in a conventional 0.18-μm CMOS technology. The proposed concepts were validated by correlating RF measurements at 1 GHz with the measured dc voltage output of the on-chip sensor and the simulation results, demonstrating that the RF power dissipation can be monitored and the 1-dB compression point can be estimated with less than 1-dB error. The sensor circuitry occupies a die area of 0.012 mm², which can be shared when several on-chip locations are observed by placement of multiple temperature-sensing parasitic bipolar devices.

Systolic array architectures have recently emerged as successful accelerators for deep convolutional neural network (CNN) inference. Such architectures can be used to efficiently execute general matrix–matrix multiplications (GeMMs), but computing convolutions with this primitive involves transforming the 3-D input tensor into an equivalent matrix, which can lead to an inflation of the input data, increasing the OFF-chip memory traffic which is critical for energy efficiency. In this work, we propose a GeMM-based systolic array accelerator that uses a novel data feeder architecture to perform ON-chip, on-the-fly convolution lowering (also known as im2col), supporting arbitrary tensor and kernel sizes as well as strided and dilated (or atrous) convolutions. By using our data feeder, we reduce memory transactions and required bandwidth on state-of-the-art CNNs by a factor of two, while only adding an area and power overhead of 4% and 7%, respectively. Application specific integrated circuit (ASIC) implementation of our accelerator in 22-nm technology fits in less than 1.1 mm 2 and reaches an energy efficiency of 1.10 TFLOP/sW with 16-bit floating-point arithmetic.