Ethernet is the dominant wireline communications technology for LANs with over 1 billion interfaces installed in the U.S. and over 3 billion worldwide. In 2006 the IEEE 802.3 Working Group started an effort to improve the energy efficiency of Ethernet. This effort became IEEE P802.3az Energy Efficient Ethernet (EEE) resulting in IEEE Std 802.3az-2010, which was approved September 30, 2010. EEE uses a Low Power Idle mode to reduce the energy consumption of a link when no packets are being sent. In this article, we describe the development of the EEE standard and how energy savings resulting from the adoption of EEE may exceed $400 million per year in the U.S. alone (and over $1 billion worldwide). We also present results from a simulation-based performance evaluation showing how packet coalescing can be used to improve the energy efficiency of EEE. Our results show that packet coalescing can significantly improve energy efficiency while keeping absolute packet delays to tolerable bounds. We are aware that coalescing may cause packet loss in downstream buffers, especially when using TCP/IP. We explore the effects of coalescing on TCP/IP flows with an ns-2 simulation, note that coalescing is already used to reduce packet processing load on the system CPU, and suggest open questions for future work. This article will help clarify what can be expected when EEE is deployed.

Until very recently, energy efficiency has received little attention in many wired communications environments. For example, in most current Ethernet standards the transmitter and receiver operate at full power even when no data is being sent. However, new upcoming energy-aware standards, such as Energy Efficient Ethernet (EEE), are addressing this issue by introducing a low power mode for idle link intervals. The future EEE standard defines the procedure to enter and exit the low power mode. With EEE the actual energy savings will depend on the amount of traffic and on the timing of the frame arrivals. In this paper the performance of EEE in terms of energy saving is evaluated. The results show that although EEE improves the energy efficiency, there is still potential for substantial further energy savings as in many cases most of the energy is wasted in waking up and sleeping the link.

In September 2010, the Energy Efficient Ethernet (IEEE 802.3az) standard was officially approved. This new standard introduces a low power mode for the most common Ethernet physical layer standards and is expected to provide large energy savings. In this letter, for the first time, Network Interface Cards (NICs) that implement Energy Efficient Ethernet (EEE) are used to measure energy savings with real traffic. The data presented will be useful to better estimate the energy savings that can be achieved when EEE is deployed. Existing analysis of EEE based on simulations predict a large overhead due to mode transitions between active and low power modes. The experimental results confirm that transition overheads can be significant, leading to almost full energy consumption even at low utilization levels. Therefore traffic patterns will play a key role in the energy savings achieved by EEE as it becomes deployed in the field.

Nowadays, single event upsets (SEUs) altering digital circuits are becoming a bigger concern for memory applications. This paper presents an error-detection method for difference-set cyclic codes with majority logic decoding. Majority logic decodable codes are suitable for memory applications due to their capability to correct a large number of errors. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low.

The reliability of memory systems that are exposed to soft errors has been studied in the past with the aim of deriving the mean time to failure (MTTF) and the probability of failing in a given time interval. On those studies, the soft errors were considered to arrive following a Poissonian basis and they were assumed to be single uncorrelated events (each event causes only one soft error). Recent studies suggest that multiple bit upsets (MBUs) are a significant part of the error events in advanced memory technologies and that they will continue to grow in the next technology nodes. The errors in an MBU are normally caused by the same physical event and therefore affect memory cells that are close together. This poses a major problem to memories that are protected with per-word single error correction codes, as an MBU is likely to affect two or more bits in the same word, causing an uncorrectable error. To avoid that problem, interleaving is used to ensure that cells that are physically close together belong to different logical words, so that the errors in an MBU are distributed over a number of words each suffering only one error. Although some works have been done that characterize memories under radiation tests, no mathematical model of the effect of MBUs on the reliability of a memory has been proposed in the literature, to the best of the authors' knowledge. Therefore, in this paper, the reliability of memories suffering MBUs is analyzed in detail. The fundamental result from that analysis is that the MTTF of a memory exposed to MBUs can be approximated using the existing results for single event upsets by adjusting the error arrival rate.

Radiation particles can impact registers or memories creating soft errors. These errors can modify more than one bit causing a multiple cell upset (MCU) which consists of errors in registers or memory cells that are physically close. These MCUs can affect a single word, producing adjacent bit errors. Hamming codes are commonly used to protect memories or registers from soft errors. However, when multiple errors occur, a Hamming code may not detect them. In this letter, single-error-correction double adjacent error detection Hamming codes are presented for 16-, 32-, and 64-bit words. Additionally, single-error-correction double-error-detection triple adjacent error detection codes based on extended Hamming are presented as well. The enhanced detection is achieved by performing a selective shortening and reordering of the Hamming matrix so adjacent errors result in a syndrome that does not match that of any single error. These codes will help in the detection of MCUs in SRAM memory designs.