Dominance of various scattering mechanisms in determination of the carrier mobility is examined for silicon (Si) nanowires of sub-10-nm cross-sections. With a focus on p-type channels, the steady-state hole mobility is studied with multi-subband Monte Carlo simulations to consider quantum effects in nanoscale channels. Electronic structures of gate-all-around nanowires are described with a 6-band k · p model. Channel bandstructures and electrostatics under gate biases are determined self-consistently with Schrödinger-Poisson simulations. Modeling results not only indicate that the hole mobility is severely degraded as channels have smaller cross-sections and are inverted more strongly but also confirm that the surface roughness scattering degrades the mobility more severely than the phonon scattering does. The surface roughness scattering affects carrier transport more strongly in narrower channels, showing ∼90 % dominance in determination of the mobility. At the same channel population, [110] channels suffer from the surface roughness scattering more severely than [100] channels do, due to the stronger corner effect and larger population of carriers residing near channel surfaces. With a sound theoretical framework coupled to the spatial distribution of channel carriers, this work may present a useful guideline for understanding hole transport in ultra-narrow Si nanowires.

Quantum logic operations and electron spin controls in a Si double quantum dot platform is studied with a multi-scale modeling approach that can open the pathway to explore engineering details for Si-based designs of robust quantum logic gates.

Modelling of multi-million atomic semiconductor structures is important as it not only predicts properties of physically realizable novel materials, but can accelerate advanced device designs. This work elaborates a new Technology-Computer-Aided-Design (TCAD) tool for nanoelectronics modelling, which uses a sp3d5s∗ tight-binding approach to describe multi-million atomic structures, and simulate electronic structures with high performance computing (HPC), including atomic effects such as alloy and dopant disorders. Being named as Quantum simulation tool for Advanced Nanoscale Devices (Q-AND), the tool shows nice scalability on traditional multi-core HPC clusters implying the strong capability of large-scale electronic structure simulations, particularly with remarkable performance enhancement on latest clusters of Intel Xeon PhiTM coprocessors. A review of the recent modelling study conducted to understand an experimental work of highly phosphorus-doped silicon nanowires, is presented to demonstrate the utility of Q-AND. Having been developed via Intel Parallel Computing Center project, Q-AND will be open to public to establish a sound framework of nanoelectronics modelling with advanced HPC clusters of a many-core base. With details of the development methodology and exemplary study of dopant electronics, this work will present a practical guideline for TCAD development to researchers in the field of computational nanoelectronics

The quality of quantum bits (qubits) in silicon is highly vulnerable to charge noise that is omnipresent in semiconductor devices and is in principle hard to be suppressed. For a realistically sized quantum dot system based on a silicon-germanium heterostructure whose confinement is manipulated with electrical biases imposed on top electrodes, we computationally explore the noise-robustness of 2-qubit entangling operations with a focus on the controlled-X (CNOT) logic that is essential for designs of gate-based universal quantum logic circuits. With device simulations based on the physics of bulk semiconductors augmented with electronic structure calculations, we not only quantify the degradation in fidelity of single-step CNOT operations with respect to the strength of charge noise, but also discuss a strategy of device engineering that can significantly enhance noise-robustness of CNOT operations with almost no sacrifice of speed compared to the single-step case. Details of device designs and controls that this work presents can establish practical guideline for potential efforts to secure silicon-based quantum processors using an electrode-driven quantum dot platform.

We design a variational quantum algorithm (VQA) to solve multi-dimensional Poisson equations with mixed boundary conditions that are typically required in various fields of computational science. Employing an objective function that is formulated with the concept of the minimal potential energy, we not only present in-depth discussion on the cost-efficient & noise-robust design of quantum circuits that are essential for evaluation of the objective function, but, more remarkably, employ the proposed algorithm to calculate bias-dependent spatial distributions of electric fields in semiconductor systems that are described with a two-dimensional domain and up to 10-qubit circuits. Extending the application scope to multi-dimensional problems with mixed boundary conditions for the first time, fairly solid computational results of this work clearly demonstrate the potential of VQAs to tackle Poisson equations derived from physically meaningful problems.