Md Jubaer Hossain Pantho

Mr. Md Jubaer Hossain Pantho

University of Florida
orcid

Research Focus & Metrics

Academic Career Length

9Years (2018-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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10 March 2021 in Sensors
Verified
Journal Article
Open access
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Md Jubaer Hossain PanthoMd Jubaer Hossain Pantho
Md Jubaer Hossain Pantho
PBPankaj Bhowmik
Pankaj Bhowmik
Christophe BobdaChristophe Bobda
Christophe Bobda
The astounding development of optical sensing imaging technology, coupled with the impressive improvements in machine learning algorithms, has increased our ability to understand and extract information from scenic events. In most cases, Convolution neural networks (CNNs) are largely adopted to infer knowledge due to their surprising success in automation, surveillance, and many other application domains. However, the convolution operations’ overwhelming computation demand has somewhat limited their use in remote sensing edge devices. In these platforms, real-time processing remains a challenging task due to the tight constraints on resources and power. Here, the transfer and processing of non-relevant image pixels act as a bottleneck on the entire system. It is possible to overcome this bottleneck by exploiting the high bandwidth available at the sensor interface by designing a CNN inference architecture near the sensor. This paper presents an attention-based pixel processing architecture to facilitate the CNN inference near the image sensor. We propose an efficient computation method to reduce the dynamic power by decreasing the overall computation of the convolution operations. The proposed method reduces redundancies by using a hierarchical optimization approach. The approach minimizes power consumption for convolution operations by exploiting the Spatio-temporal redundancies found in the incoming feature maps and performs computations only on selected regions based on their relevance score. The proposed design addresses problems related to the mapping of computations onto an array of processing elements (PEs) and introduces a suitable network structure for communication. The PEs are highly optimized to provide low latency and power for CNN applications. While designing the model, we exploit the concepts of biological vision systems to reduce computation and energy. We prototype the model in a Virtex UltraScale+ FPGA and implement it in Application Specific Integrated Circuit (ASIC) using the TSMC 90nm technology library. The results suggest that the proposed architecture significantly reduces dynamic power consumption and achieves high-speed up surpassing existing embedded processors’ computational capabilities.

5 January 2022 in Journal of Real-Time Image Processing
Verified
Journal Article
Open access
PDF file
Md Jubaer Hossain PanthoMd Jubaer Hossain Pantho
Md Jubaer Hossain Pantho
JMJoel Mandebi Mbongue
Joel Mandebi Mbongue
PBPankaj Bhowmik
Pankaj Bhowmik
Christophe BobdaChristophe Bobda
Christophe Bobda
In recent years, there has been a growing interest in realizing methodologies to integrate more and more computation at the level of the image sensor. The rising trend has seen an increased research interest in developing novel event cameras that can facilitate CNN computation directly in the sensor. However, event-based cameras ca be expensive, limiting performance exploration on high-level models and algorithms. This paper presents an event camera simulator that can be a potent tool for hardware design prototyping, parameter optimization, attention-based innovative algorithm development, and benchmarking. The proposed simulator implements a distributed computation model to identify relevant regions in an image frame. Our simulator’s relevance computation model is realized as a collection of modules and performs computations in parallel. The distributed computation model is configurable, making it highly useful for design space exploration. The Rendering engine of the simulator samples frame-regions only when there is a new event. The simulator closely emulates an image processing pipeline similar to that of physical cameras. Our experimental results show that the simulator can effectively emulate event vision with low overheads

4 March 2021 in Sensors
Verified
Journal Article
Open access
PDF file
PBPankaj Bhowmik
Pankaj Bhowmik
Md Jubaer Hossain PanthoMd Jubaer Hossain Pantho
Md Jubaer Hossain Pantho
Christophe BobdaChristophe Bobda
Christophe Bobda
Cameras are widely adopted for high image quality with the rapid advancement of complementary metal-oxide-semiconductor (CMOS) image sensors while offloading vision applications’ computation to the cloud. It raises concern for time-critical applications such as autonomous driving, surveillance, and defense systems since moving pixels from the sensor’s focal plane are expensive. This paper presents a hardware architecture for smart cameras that understands the salient regions from an image frame and then performs high-level inference computation for sensor-level information creation instead of transporting raw pixels. A visual attention-oriented computational strategy helps to filter a significant amount of redundant spatiotemporal data collected at the focal plane. A computationally expensive learning model is then applied to the interesting regions of the image. The hierarchical processing in the pixels’ data path demonstrates a bottom-up architecture with massive parallelism and gives high throughput by exploiting the large bandwidth available at the image source. We prototype the model in field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) for integrating with a pixel-parallel image sensor. The experiment results show that our approach achieves significant speedup while in certain conditions exhibits up to 45% more energy efficiency with the attention-oriented processing. Although there is an area overhead for inheriting attention-oriented processing, the achieved performance based on energy consumption, latency, and memory utilization overcomes that limitation.

1 April 2018
Verified
Conference Paper
Closed access
Md Jubaer Hossain PanthoMd Jubaer Hossain Pantho
Md Jubaer Hossain Pantho
JMJoel Mandebi Mbongue
Joel Mandebi Mbongue
CBChristophe Bobda
Christophe Bobda
DADavid Andrews
David Andrews
MAMarjan Asadinia
Marjan Asadinia
This paper presents a CPU-FPGA heterogeneous system that provides hardware support for computer vision libraries to attain acceleration over image processing applications. The architecture achieves this improvement by staying completely transparent to the developer while providing necessary acceleration on conventional software designs.

13 February 2020 in arXiv
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Preprint
Open access
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WTWilly Carlos Tchuitcheu
Willy Carlos Tchuitcheu
Christophe BobdaChristophe Bobda
Christophe Bobda
Md Jubaer Hossain PanthoMd Jubaer Hossain Pantho
Md Jubaer Hossain Pantho
Smart and decentralized control systems have recently been proposed to handle the growing traffic congestion in urban cities. Proposed smart traffic light solutions based on Wireless Sensor Network and Vehicular Ad-hoc NETwork are either unreliable and inflexible or complex and costly. Furthermore, the handling of special vehicles such as emergency is still not viable, especially during busy hours. Inspired by the emergence of distributed smart cameras, we present a novel approach to traffic control at intersections. Our approach uses smart cameras at intersections along with image understanding for real-time traffic monitoring and assessment. Besides understanding the traffic flow, the cameras can detect and track special vehicles and help prioritize emergency cases. Traffic violations can be identified as well and traffic statistics collected. In this paper, we introduce a flexible, adaptive and distributed control algorithm that uses the information provided by distributed smart cameras to efficiently control traffic signals. Experimental results show that our collision-free approach outperforms the state-of-the-art of the average user's waiting time in the queue and improves the routing of emergency vehicles in a cross congestion area.

1 November 2020 in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Verified
Journal Article
Closed access
Md Jubaer Hossain PanthoMd Jubaer Hossain Pantho
Md Jubaer Hossain Pantho
Christophe BobdaChristophe Bobda
Christophe Bobda