This paper presents a framework for converting P4 programs to VHDL and then implementing them on Field-Programmable Gate Array (FPGA) platforms. In this framework, a match-action-based hardware architecture is introduced with clearly designed components, which correspond to the described functionalities in the P4 programs. A pre-built template library is used for the compilation that includes optimized VHDL templates corresponding to specific clearly designed components. From the output of a standard frontend P4 compiler, the proposed compiler extracts parameters and relationships within the functions being employed, maps them to corresponding templates by calling, configuring, optimizing and instantiating them, and finally generates the appropriate FPGA code. A pre-built evaluation library is also proposed that helps the compiler to optimize the implementation during the mapping phase. A prototype of this framework is also implemented and evaluated; in this process, it is found that the generated processors use few resources and have high throughput and low latency. Compared with a state-of-the-art solution, the packet processing time is halved. In addition, the generated processors are able to operate at a line rate of nearly 100 Gigabits per second for a basic layer-3 forwarding application.

The development of modern networking requires that high-performance network processors be designed quickly and efficiently to support new protocols. As a very important part of the processor, the parser parses the headers of the packets—this is the precondition for further processing and finally forwarding these packets. This paper presents a framework designed to transform P4 programs to VHDL and to generate parsers on Field Programmable Gate Arrays (FPGAs). The framework includes a pipeline-based hardware architecture and a back-end compiler. The hardware architecture comprises many components with varying functionality, each of which has its own optimized VHDL template. By using the output of a standard frontend P4 compiler, our proposed compiler extracts the parameters and relationships from within the used components, which can then be mapped to corresponding templates by configuring, optimizing, and instantiating them. Finally, these templates are connected to output VHDL code. When a prototype of this framework is implemented and evaluated, the results demonstrate that the throughputs of the generated parsers achieve nearly 320 Gbps at a clock rate of around 300 MHz. Compared with state-of-the-art solutions, our proposed parsers achieve an average of twice the throughput when similar amounts of resources are being used.

Modern electronic systems impose strict requirements on clock accuracy and stability. To address this, this paper proposes a high-precision clock generation and retention method based on GNSS timing and all-digital control logic. Taking GNSS second pulse (1PPS) as a high-precision reference, a fully digital closed-loop control system based on heterogeneous computing platforms was constructed to achieve highly integrated hardware and flexible deployment of algorithms. In the control strategy, a Model Reference Adaptive Control (MRAC) algorithm was designed to estimate and compensate the nonlinear and time-varying characteristics of OCXO tuning sensitivity in real time, thereby enhancing the frequency control accuracy. In view of the loss of external reference time, a semi-parametric aging prediction model combining physical prior and lightweight Multilayer Perceptron (MLP) was used to actively predict the frequency drift and compensate the voltage, so as to prolong the high-precision retention time of the clock. Experimental results show that the proposed system can improve the long-term stability of the OCXO output clock to the order of 10−13, and maintain the clock accuracy in the sub-ppb (part per billion) accuracy range for several hours after GNSS loss, which effectively enhances the reliability and adaptability of the clock system under the abnormal reference signal. This study provides an integrated and intelligent solution for the design of high-precision clock sources, which is suitable for application scenarios with stringent time synchronization requirements in communication, navigation, finance and other fields.