This brief presents an efficient sorting architecture for successive-cancellation-list decoding of polar codes. In order to avoid performing redundant sorting operations on the metrics that are already sorted in the previous step of decoding, the proposed architecture separately processes the sorted metrics and unsorted ones. In addition, the odd–even sort network is adopted as a basic building block to further reduce the hardware complexity while sustaining low latencies for various list sizes. On average, the proposed architecture requires less than 50% of the compare-and-swap units demanded by the area-efficient sorting networks in the literature.

Deep neural network (DNN)-based object detection has been investigated and applied to various real-time applications. However, it is hard to employ the DNNs in embedded systems due to their high computational complexity and deep-layered structure. Although several field-programmable gate array (FPGA) implementations have been presented recently for real-time object detection, they suffer from either low throughput or low detection accuracy. In this article, we propose an efficient computing system for real-time SSDLite object detection on FPGA devices, which includes novel hardware architecture and system optimization techniques. In the proposed hardware architecture, a neural processing unit (NPU) that consists of heterogeneous units, such as band processing, scaling, and accumulating, and data fetching and formatting units is designed to accelerate the DNNs efficiently. In addition, system optimization techniques are presented to improve the throughput further. A task control unit is employed to balance the workload and increase the utilization of heterogeneous units in the NPU, and the object detection algorithm is refined accordingly. The proposed architecture is realized on an Intel Arria 10 FPGA and enhances the throughput by up to 13.6× compared to the state-of-the-art FPGA implementation.

Allowing the superior error-correction performance even for short-length codewords, the successive-cancellation list (SCL) decoding algorithm has allowed the polar code to be adopted in 5G New Radio standard for control channel. However, existing SCL polar decoders still suffer from long processing latency caused by a number of serialized internal operations. In this work, to solve the latency problem, we present several parallel computing solutions for the serialized operations, i.e., simplified data dependencies and two overlapped pruning operations. To realize the proposed parallel computing, we also introduce internal circuit blocks including dual read-port buffers, an on-the-fly parity checker, and overlapped processing units. The proposed SCL polar decoders are precisely designed with optimal design parameters by analyzing trade-offs between the latency reduction and area overheads. Implemented in a 65-nm CMOS technology, the proposed list-8 SCL polar decoder requires only 374 ns to handle a (1024, 512) 5G codeword, improving the decoding efficiency by 34.7% compared to the previous designs.

This brief presents an improved sorting architecture for K-best multiple-input multiple-output (MIMO) detection. In the proposed architecture, two properties of the K-best MIMO detection are exploited for simplifications: the order among siblings from the same parent node can be easily identified; the order among the K-best nodes is dispensable. Besides, the generalized mergesort-based architecture for the K-best sorting is presented so that the proposed sorter can be constructed for any power-of-two K and modulation scheme. Compared to the conventional ones, the proposed architecture lowers not only the hardware complexity but also the latency significantly.

This article presents an approximate signed digit representation (ASD) which quantizes the weights of convolutional neural networks (CNNs) in order to make multiplier-less CNNs without performing any retraining process. Unlike the existing methods that necessitate retraining for weight quantization, the proposed method directly converts full-precision weights of CNN models into low-precision ones, attaining accuracy comparable to that of full-precision models on the Image classification tasks without going through retraining. Therefore, it is effective in saving the retraining time as well as the related computational cost. As the proposed method simplifies the weights to have up to two non-zero digits, multiplication can be realized with only add and shift operations, resulting in a speed-up of inference time and a reduction of energy consumption and hardware complexity. Experiments conducted for famous CNN architectures, such as AlexNet, VGG-16, ResNet-18 and SqueezeNet, show that the proposed method reduces the model size by 73% at the cost of a little increase of error rate, which ranges from 0.09% to 1.5% on ImageNet dataset. Compared to the previous architecture built with multipliers, the proposed multiplier-less convolution architecture reduces the critical-path delay by 52% and mitigates the hardware complexity and power consumption by more than 50%.

A practical min-sum algorithm is associated with tree-based comparison units for the check-node operation, being a major bottleneck in designing low-cost and energy-efficient low-density parity-check (LDPC) decoders. In this brief, we present a cost-effective LDPC decoder architecture by changing its internal computing resolution for the power-hungry check-node processing. The proposed mixed-resolution comparison offers significant advantages in terms of both area and energy, while achieving error-correcting performance within 0.3 dB of the previous normalized min-sum (NMS) algorithm for a (1644, 1408) quasi-cyclic LDPC code of the 5G New Radio specifications. Compared to the baseline NMS architecture, the proposed decoder in a 65-nm CMOS technology reduces the hardware complexity and the power consumption by 28.4% and 23.1%, respectively, enhancing the area efficiency by more than 88.2%.