The main idea behind this project is to provide a unified platform which will cover a complete process for embedded systems learning. A modular approach is considered for skills practice through supporting individualization in learning. This platform shall facilitate a novel development of universal approach in creative learning environment and knowledge management that encourage use of ICT. New learning model is challenging the education of engineers in embedded systems design through real-time experiments that stimulate curiosity with ultimate goal to support students to understand and construct their personal conceptual knowledge based on experiments. In addition to the technological approach, the use of cognitive theories on how people learn will help students to achieve a stronger and smarter adaptation of the subject. Applied methodology will be evaluated from the scientific point of view in parallel with the implementation in order to feedback results to the R&D.

The current verification methodologies on the final production line in digital television industry require a significant amount of manual work in connecting and disconnecting the television set to and from signal sources and verifying the correctness and quality of image shown on the TV screen. This manual work slows down the production and increases the cost of a final production line. This paper proposes an automatic system which will perform all required verification steps on the final production line such that manual work will be minimized, speed of the production will significantly increase and the cost of the final production line will decrease. The proposed final production line uses the camera to capture the image shown on the TV screen which improves the earlier solution with the grabber to allow verification of the image quality as seen by the user. The proposed system consists of: (1) TV set being verified, (2) camera to capture the content on the TV screen, (3) signal generator, (4) test monitoring system and (5) PC which runs the algorithm for extraction of the TV screen content and comparison with the referent content. The proposed algorithm uses the block-based normalized cross-correlation to compare captured and referent content. The proposed testing methodology divides the verification on the final production line in three steps: (1) setup phase, during which the TV set is brought and connected to the signal sources and test monitoring system, (2) execution phase which captures the content on the TV screen and runs the PC algorithm and (3) test report phase which reports the pass/fail result of the test in the test monitoring system. The experimental results of the block-based comparison method show a better sensitivity to small differences than the non-block-based method. The time required for verification step increased by a factor of 5 when using the automatic approach on the final production line instead of a manual one.

This paper presents one implementation of the Open Control Protocol (OCP) monitoring on the synthesized FPGA design using the implemented library of Synthesizable SystemVerilog Assertions (SSVA). The SSVA library is developed using the layer structure of SystemVerilog assertions. It is used in implementation of the monitors for two profiles of the OCP. SSVA library and OCP monitors are then functionally verified in simulator using the test case of the processor-memory communication. The test case is then synthesized on CHIPit Platinum Edition FPGA. The implemented library and monitors can be used in many commercial and educational projects due to their simplicity and low FPGA area usage.