Photonic neuromorphic computing is raising a growing interest as it promises to provide massive parallelism and low power consumption. In this paper, we demonstrate for the first time a feed-forward neural network via an 8x8 Indium Phosphide cross-connect chip, where up to 8 on-chip weighted addition circuits are co-integrated, based on semiconductor optical amplifier technology. We perform the weight calibration per neuron, resulting in a normalized root mean square error smaller than 0.08 and a best case dynamic range of 27 dB. The 4:1 weighted addition operation is executed on-chip and is part of a neuron whose non-linear function is implemented via software. A three feedback loop optimization procedure is demonstrated to enable an output neuron accuracy improvement of up to 55%. The exploitation of this technology as the neural network is evaluated by implementing a trained 3-layer photonic deep neural network to solve the Iris flower classification problem. Prediction accuracy of 85.8% is achieved, with respect to the 95% accuracy obtained via a computer. A comprehensive analysis of the error evolution in our system reveals that the electrical/optical conversions dominate the error contribution, which suggests that an all optical approach is preferable for future neuromorphic computing hardware design.

We demonstrate the use of a wavelength converter, based on cross-gain modulation in a semiconductor optical amplifier (SOA), as a nonlinear function co-integrated within an all-optical neuron realized with SOA and wavelength-division multiplexing technology. We investigate the impact of fully monolithically integrated linear and nonlinear functions on the all-optical neuron output with respect to the number of synapses/neuron and data rate. Results suggest that the number of inputs can scale up to 64 while guaranteeing a large input power dynamic range of 36 dB with neglectable error introduction. We also investigate the performance of its nonlinear transfer function by tuning the total input power and data rate: The monolithically integrated neuron performs about 10% better in accuracy than the corresponding hybrid device for the same data rate. These all-optical neurons are then used to simulate a 64:64:10 two-layer photonic deep neural network for handwritten digit classification, which shows an 89.5% best-case accuracy at 10 GS/s. Moreover, we analyze the energy consumption for synaptic operation, considering the full end-to-end system, which includes the transceivers, the optical neural network, and the electrical control part. This investigation shows that when the number of synapses/neuron is >18, the energy per operation is <20 pJ (6 times higher than when considering only the optical engine). The computation speed of this two-layer all-optical neural network system is 47 TMAC/s, 2.5 times faster than state-of-the-art graphics processing units, while the energy efficiency is 12 pJ/MAC, 2 times better. This result underlines the importance of scaling photonic integrated neural networks on chip.

As the global internet protocol (IP) traffic volume growth puts more pressure on network connectivity, bandwidth and latency requirements, crucial network elements such as switches need continuous improvement. To this end, we report a monolithically integrated, ultra-compact 8×8 optical space switch based on semiconductor optical amplifier (SOA) gates, utilizing ultra-compact bends and denser SOA placement and demonstrating a strictly non-blocking broadcast and select (B&S) switch architecture on-chip. The switch circuitry comprises 80 SOAs, 112 multimode interference (MMI) splitters, and hundreds of waveguide bends and crossings integrated onto a 4.6×8 mm ² generic indium phosphide (InP) die with I/O access on the same side. In addition, the SOA waveguide geometry is specifically optimized to improve output saturation power by 2 dB and enable WDM operation. The physical layer characterization shows lossless operation on-chip due to the three SOAs in a path that provides enough gain to compensate for on-chip passive losses. The best-case OSNR is higher than 40 dB. We perform static data signal routing with four-channel wavelength division multiplexed (WDM) data signals at 25 Gb/s and 35 Gb/s, resulting in a worst-case 2 dB power penalty on receiver sensitivity. Additionally, we dynamically switch data signals at bit rates up to 35 Gb/s obtaining a power penalty similar to the static routing. The recorded rising and falling times are 4 and 6.4 ns, respectively, suggesting this chip is suitable for packet-scale fast switching applications.

Convolutional neural network (CNN) is one of the best neural network structures for solving classification problems. The convolutional processing of the network dominates processing time and computing power. Parallel computing for convolutional processing is essential to accelerate the computing speed of the neural network. In this paper, we introduce another domain of parallelism on top of the already demonstrated parallelisms suggested for photonic integrated processors with WDM approaches, to further accelerate the convolutional operation on chip. The operation of the novel parallelism is introduced with an updated cross-connect architecture, exploiting cyclic array waveguide grating. The photonic CNN system is demonstrated for the handwritten digit classification problem in simulation, with a speed of 2.56 Tera operation/s and end-to-end system energy efficiency of 3.75 pJ/operation, using 16 weighting elements and 10 Giga sample/s inputs. The proposed parallelism improves CNN acceleration by 4-16 times with respect to state-of-the-art integrated convolutional processors, depending on the available weighting elements per convolutional core.

Low‐profile and wideband gain enhancement Fabry–Perot cavity antennas (FPCA) is proposed using gradient Partially Reflective Surface (PRS) and gradient Artificial Magnetic Conductor (AMC). A wideband source antenna is designed with a −10 dB impedance bandwidth of 58.1% (6.1–11.1 GHz). The PRS is constructed by a complementary frequency‐Selective Surfaces (FSS) with a square hole and four small patches in a unit, which realizes phase increasing with frequency. The PRS and the AMC are gradient alone x ‐direction to achieve wideband phase compensation. While they are uniform in y ‐direction to realize better gain enhancement. Compared with the source antenna, the gain enhancement of the proposed FPCA is about 4–7 dBi. Moreover, the simulated and measured 3‐dB gain bandwidths are 7.26–10.33 GHz (34.8%) and 6.8–10.8 GHz (46%), respectively. The gain enhanced bandwidth is about 52.3% (6.5–11.1 GHz). The impedance bandwidth is 6–11.1 GHz (59.65%). By using the gradient size AMC, the profile of the FPCA is reduced from 0.5 λ ₀ to 0.2 λ ₀ , where λ ₀ is the wavelength of 8.5 GHz. The proposed FPCA has the characteristics of wide impedance bandwidth, wide 3‐dB gain bandwidth, wide gain enhanced bandwidth and low‐profile.

Ge epilayers of different thicknesses are grown by molecular-beam epitaxy with Sb as a surfactant on Si(100) substrates. X-ray diffraction illustrates that these Ge thin films are partially strained, and the strains decrease gradually with increasing epilayer thickness. Raman spectra reveal a downward shift of the Ge–Ge mode peak as the epilayer thickness increases. In the regions of high strain, the relationship between the Raman shift of this mode and the strain in the partially relaxed samples is considerably different from the linear relationship reported before, which is mainly attributed to the spatial confinement effect of phonons in a nanocrystal.