In this paper, we propose a high-sensitivity optical sensor at terahertz frequencies based on a composite structure containing a one-dimensional photonic crystal (1D PC) coated with a layer of monolayer graphene. Between the 1D PC and the graphene there is a sensing medium. This high-sensitivity phenomenon originates from the excitation of optical resonance between the graphene and the 1D PC. The proposed sensor is highly sensitive to the Fermi energy of graphene, the thickness and refractive index of the sensing medium, and the number of graphene layers. By selecting appropriate parameters, the maximum sensitivity ( ${407.36}^{\circ }/\mathrm{RIU}$ ) is obtained. We believe the proposed configuration is promising for fabricating graphene-based biosensor- or gas-sensor devices and other related applications in the terahertz band.

In industrial-grade bus, transient voltage suppressor (TVS) devices that need to withstand inrush currents ensure ESD reliability of the core chip. This paper designs four types of dual direction silicon controlled rectifiers(DDSCR) device structures based on 0.5μm CMOS process. The ESD performance of the TVS device is predicted and verified based on the basic principles of the device, 2D device simulation and transmission line pulse(TLP) test results. Four DDSCR structures are embedded with floating N+ to adjust the device's holding voltage window. The results show that the current release capacity of DDSCR_1 is 81.93 mA/μm. The current release capability of DDSCR_2 which has a double dummy gate structure is 82.37 mA/μm. The current release capability of the DDSCR_3 of the gate-controlled structure is 86.68 mA/μm. The current release capability of the DDSCR_4 of the double dummy gate structure and gate-controlled structure is 86.25 mA/μm. Furthermore, the effect of the size of these devices on the ESD characteristics was studied. The on-resistance of the device structure was calculated by the curve fitting method. The influence of the dummy gate structure and the gate-controlled structure on the ESD characteristics was analyzed. Finally, the optimal device size to meet the window was found.

In this article, a dual loop-compensated, fast-transient, low-dropout regulator (LDO) is proposed for battery-powered applications. It is successfully implemented in a 0.18-μm CMOS process with a total silicon area of 210 μm x 593 μm. The proposed LDO is composed of two feedback loops. The fast feedback loop (FFL) employs direct output voltage spike detection through capacitive coupling, resulting in significantly improved, large signal transient response and loop bandwidth at the same time. Its voltage spike is 15 mV for a load step of 600 mA. The proposed LDO has a loop bandwidth of 2.3 MHz at a load current of 600 mA with a 30-μA no-load bias current. A power transistor with pseudo-equivalent series resistance (ESR) technique is proposed for loop stability improvement. It enables the usage of the low-cost, multilayer ceramic capacitors in mobile applications. The constant biased voltage feedback loop (VFL) has a loop gain larger than 60 dB under all load conditions, which enables a good line and load regulation.

Single photon avalanche diodes(SPAD) based on avalanche effect have been widely used in the detection of extremely weak light signals. Conventional SPAD devices manufactured with silicon-based CMOS technology have a high dark count rate(DCR), making it difficult to accurately detect single photon signals. This paper proposes a low dark count rate ring-gate SPAD(RG-SPAD) to solve above problems, and compares RG-SPAD with conventional SPAD(C-SPAD) and conventional dummy-gate SPAD(CDG-SPAD). Slivaco-Technology Computer Aided Design(TCAD) performs two-dimensional simulation of the device to verify the basic principles of SPAD. Three types of SPAD device are manufactured by standard BCD process. The passive quenching circuit is built to obtain the DCR of SPAD devices. The avalanche breakdown voltages of C-SPAD, CDG-SPAD and RG-SPAD are 11.55V, 11.85V and 11.4V respectively. In order to test the dark count rate of SPAD devices, an over-bias voltage of 1V was applied to three types of SPAD device under the same size condition(temperature: 22°C). The DCR of RG-SPAD(186Hz) with ring-gate structure is significantly lower than CDG-SPAD(378Hz) with conventional dummy-gate structure and C-SPAD(498Hz) with conventional structure. When the room temperature dropped to 18°C, RG-SPAD still maintained the lowest DCR(148Hz) among three types of device structure.