During pulse signal collection, width information of pulse waves is essential for the diagnosis of disease. However, currently used measuring instruments can only detect the amplitude while can’t acquire the width information. This paper proposed a novel wrist pulse signal acquisition system, which could realize simultaneous measurements of the width and amplitude of dynamic pulse waves under different static forces. A tailor-packaged micro-electro-mechanical system (MEMS) sensor array was employed to collect pulse signals, a conditioning circuit was designed to process the signals, and a customized algorithm was developed to compute the width. Experiments were carried out to validate the accuracy of the sensor array and system effectiveness. The results showed the system could acquire not only the amplitude of pulse wave but also the width of it. The system provided more information about pulse waves, which could help doctors make the diagnosis.

Due to a variety of limitations on the system-on-chip (SoC), the microelectronics industry is now facing challenges and making slow progress in recent years. With architecture design and advanced packaging advantages, chiplet heterogeneous integration (CHI) systems have become a promising solution to long-lasting hardship. However, high power consumption in CHI systems generates massive heat and makes thermal design a demanding task. Therefore, an accurate tool for thermal simulation is indispensable in the design flow. In this article, a multiscale anisotropic thermal model is proposed for the CHI systems. It considers the feature-scale thermal conductivities of different materials to predict the package-scale steady-state temperature fields. Specifically, the local material composition and thermal conductivity of redistribution layers (RDLs) are extracted from design layout files by constructing an equivalent thermal conductivity algorithm of local feature structures. As for through silicon via (TSV) and bump arrays, the anisotropic distributions of thermal conductivity can also be derived with equivalent algorithms. Other structures are considered homogeneous blocks to significantly reduce the computational expense without losing the generality of the proposed model. Compared with the previous isotropic thermal model of CHI systems, the present multiscale anisotropic thermal model is proven to make temperature prediction and hotspot detection more reliable. With this tool, the reliability problems that are unpredictable and obscure for isotropic thermal models can be identified in advance, and more reasonable design space can be explored in the design flow of the CHI systems.

Chiplet heterogeneous integration (CHI) is one of the important technology choices to continue Moore’s law. However, due to the characteristics of high power and low supply voltage in CHI systems, heavy currents need to flow through the power delivery network (PDN), and the Joule heating effect will result in the overall temperature increase of the CHI system. Meanwhile, the high temperature will cause the current as well as the performance of the system to degrade and a series of reliability problems will occur. In this article, an effective electrical–thermal coupling model is proposed to predict the steady-state temperature distribution of a 2.5-D CHI system considering the Joule heating effect and the temperature effect on the IR drop. The equivalent electrical conductivity model is also built up to describe the design features of the redistribution layer (RDL), bump, and through silicon via (TSV) structures based on the electrical–thermal duality. Furthermore, the governing equations for voltage distribution and temperature distribution are solved simultaneously by utilizing the finite volume method (FVM) with nonuniform mesh to realize the electrical–thermal co-simulation of the multiscale CHI system. The model application is further performed to investigate the influence of the model parameters on the voltage drop and temperature distribution of the CHI system. The verified systems and simulated results of the present investigation demonstrate the viability and accuracy of voltage and temperature field co-simulation and indicate that the new proposed electrical–thermal model is helpful in thermal and voltage drop analysis of packaging structures with the Joule heating effect and can be adopted to assist in the physical design optimization of 2.5-D CHI or 3-D heterogeneous stacked chips.

This letter presents a 6-bit active vector-modulated phase shifter (VMPS) with a linearization control technique, which is implemented in a 0.13- $\mu $ m silicon-on-insulator (SOI) process. The improved balun structure and capacitance compensation polyphase filter (C-PPF) are used to achieve broadband matching and reduce orthogonal network loss while preserving orthogonal balance. A nonlinear digital-to-analog converter (DAC) cancels out the nonlinearity of a vector modulator (VM) and achieves linear control of the amplitude and phase. The VM core consists of variable gain amplifiers (VGAs) based on Gilbert cell architecture. The measured phase shifter shows minimal rms phase error of ${<}0.29^{\circ}$ and rms gain error of ${<}0.24$ dB, and the insertion loss is 0.8–3.1 dB, respectively in $X$ -band. The total power consumption is 90 mW with a 2.5 V supply voltage and occupies a core area of 0.92 mm $^{{2}}$ excluding pads.

Electronically tuned bandpass filters are crucial frequency-selective devices in tunable RF front-ends and are extensively utilized in the fields of communications and sensing. For low-cost and easy integration, varactor based tunable microstrip filters have been widely used in circuit design. The miniaturization, tuning flexibility, and performance optimization of tunable microstrip filters are all areas of concern. This paper reviews the research conducted on the varactor-diode-based tunable bandpass filters over the past decade. Numerous filters with various structures are introduced in the following sequence: frequency tuning, frequency and bandwidth tuning, transmission zero tuning, and tunable bandpass filter with special functions. The existing problems and limitations of various types of tuned filters have been discussed. The performance of several outstanding works has been analyzed and compared. Finally, the development direction of varactor-based microstrip tunable filters is objectively summarized, which will advance the research of microstrip filters.

A novel varactor circuit exhibiting a wider tuning range and a new technique for quadrature coupling of LC-Voltage Controlled Oscillator (LC-VCO) is presented and validated on a 25 GHz oscillator. The proposed varactor circuit employs distribute-biased parallel varactors with a series inductor connected at both ends of the varactor bank to extend the tuning range of the oscillator. Similarly, the quadrature coupling is accomplished by employing the 2nd harmonic, explicitly generated in the stand-alone free-running differential oscillator using frequency doubler. As an example, the Differential VCO (DVCO) is tunable between 20 GHz and 31 GHz and exhibits the best Phase Noise $\left(PN\right)$ of −100 dBc/Hz at 1 MHz offset frequency. Similarly, the Quadrature VCO (QVCO) covers 42% tuning bandwidth around 25 GHz oscillation frequency, which is significantly wider than other state-of-the-art VCOs at comparable frequencies. In addition, all the oscillators are designed in class-C to further improve their performances both in term of low power and low phase noise. The presented oscillators are designed using high-performance SiGe HBTs of the GlobalFoundries (GFs) 130 nm SiGe BiCMOS 8HP process. The presented DVCO and QVCO draw currents of approximately 10 mA and 21 mA, respectively from a 1.2 V supply.