We describe a majority-logic gate device suitable for use in developing single-electron integrated circuits. The device consists of a capacitor array for input summation and an irreversible single-electron box for threshold operation. It accepts three binary inputs and produces a corresponding output, a complementary majority-logic output, by using the change in its tunneling threshold caused by the input signals; it produces a logical 1 output if two or three of the inputs are logical 0 and a logical 0 output if two or three of the inputs are logical 1. We combined several of these gate devices to form subsystems, a shift register and a full adder, and confirmed their operation by computer simulation. The gate device is simple in structure and powerful in terms of implementing digital functions with a small number of devices. These superior features will enable the device to contribute to the development of single-electron integrated circuits.

Molecular neuromorphic devices are composed of a random and extremely dense network of single-walled carbon nanotubes (SWNTs) complexed with polyoxometalate (POM). Such devices are expected to have the rudimentary ability of reservoir computing (RC), which utilizes signal response dynamics and a certain degree of network complexity. In this study, we performed RC using multiple signals collected from a SWNT/POM random network. The signals showed a nonlinear response with wide diversity originating from the network complexity. The performance of RC was evaluated for various tasks such as waveform reconstruction, a nonlinear autoregressive model, and memory capacity. The obtained results indicated its high capability as a nonlinear dynamical system, capable of information processing incorporated into edge computing in future technologies.

This paper describes a majority-logic gate device that will be useful in developing single-electron integrated circuits. The gate device consists of two identical single-electron boxes combined to form a balanced pair. It accepts three inputs and produces a majority-logic output by using imbalances caused by the input signals; it produces a 1 output if two or three inputs are 1, and a 0 output if two or three inputs are 0. We combine these gate devices into two subsystems, a shift register and an adder, and demonstrate their operation by computer simulation. We also propose a method of fabricating the unit element of the gate device, a minute dot with four coupling arms. We demonstrate by experiments that it is possible to arrange these unit elements on a GaAs substrate, in a self-organizing manner, by means of a process technology that is based on selective-area metalorganic vapor-phase epitaxy.