Continuous memristor has been widely used in chaotic oscillating circuits and neuromorphic computing systems. However, discrete memristor and its coupling discrete map haven't been noticed yet. This paper presents a discrete memristor and constructs a general two-dimensional memristive map model by coupling the discrete memristor with an existing discrete map. The pinched hysteresis loops of the discrete memristor are demonstrated. Four examples of memristive discrete maps are provided, and their coupling strength-relied and memristor initial-boosted complex dynamics are investigated using numerical measures. The evaluation results manifest that the discrete memristor can enhance chaos complexity and its coupling maps can generate hyperchaos. Particularly, the hyperchaotic sequences can non-destructively be controlled by memristor initial state and the initial-controlled hyperchaos is robust, which are applicable to many chaos-based applications. Additionally, we develop a hardware platform to implement the memristive maps and acquire the four-channel hyperchaotic sequences. We also apply the memristive maps to the application of secure communication and the experiments show that the memristive maps display better performance than some existing discrete maps.

Regarding as a basic circuit component with special nonlinearity, memristor has been widely applied in chaotic circuits and neuromorphic circuits. However, discrete memristor (DM) has not been received much attention, yet. To this end, this paper reports a general DM model and its unified mapping model. Using the general DM model, four representations of DMs are given and their pinched hysteresis loops are exhibited. Based on the unified DM mapping model, four two-dimensional (2D) DM maps are generated and their parameter-relied and initials-relied behaviors are explored using multiple numerical measures. The results demonstrate that all the four 2D DM maps can generate hyperchaos with coexisting bi-stable or memristor initial-boosted behavior, and their sequences have excellent performance indictors. A hardware device is constructed to implement these maps and the analog voltage signals are experimentally acquired. Moreover, pseudo-random number generators (PRNGs) are designed using these DM maps and the test results show that the generated pseudo-random numbers (PRNs) have high randomness.