Nan-Sheng Huang

Mr. Nan-Sheng Huang

orcid

Research Focus & Metrics

Academic Career Length

30Years (1997-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 January 1999 in IEEE Transactions on Circuits and Systems I: Regular Papers
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Journal Article
Closed access
Teh-Lu LiaoTeh-Lu Liao
Teh-Lu Liao
NHNan-Sheng Huang
Nan-Sheng Huang


9 July 1999 in European Transactions on Electrical Power
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Journal Article
Closed access
PDF file
Teh-Lu LiaoTeh-Lu Liao
Teh-Lu Liao
NHNan-Sheng Huang
Nan-Sheng Huang

1 May 2020 in Energies
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Journal Article
Open access
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NHNan-Sheng Huang
Nan-Sheng Huang
YCYi Chung Chen
Yi Chung Chen
JLJørgen Christian Larsen
Jørgen Christian Larsen
Poramate ManoonpongPoramate Manoonpong
Poramate Manoonpong
The prediction of a high-level cognitive function based on a proactive brain–machine interface (BMI) control edge device is an emerging technology for improving the quality of life for disabled people. However, maintaining the stability of multiunit neural recordings is made difficult by the nonstationary nature of neurons and can affect the overall performance of proactive BMI control. Thus, it requires regular recalibration to retrain a neural network decoder for proactive control. However, retraining may lead to changes in the network parameters, such as the network topology. In terms of the hardware implementation of the neural decoder for real-time and low-power processing, it takes time to modify or redesign the hardware accelerator. Consequently, handling the engineering change of the low-power hardware design requires substantial human resources and time. To address this design challenge, this work proposes AHEAD: an automatic holistic energy-aware design methodology for multilayer perceptron (MLP) neural network hardware generation in proactive BMI edge devices. By taking a holistic analysis of the proactive BMI design flow, the approach makes judicious use of the intelligent bit-width identification (BWID) and configurable hardware generation, which autonomously integrate to generate the low-power hardware decoder. The proposed AHEAD methodology begins with the trained MLP parameters and golden datasets and produces an efficient hardware design in terms of performance, power, and area (PPA) with the least loss of accuracy. The results show that the proposed methodology is up to a 4X faster in performance, 3X lower in terms of power consumption, and achieves a 5X reduction in area resources, with exact accuracy, compared to floating-point and half-floating-point design on a field-programmable gate array (FPGA), which makes it a promising design methodology for proactive BMI edge devices.

28 November 2002
Verified
Conference Paper
Closed access
Teh-Lu LiaoTeh-Lu Liao
Teh-Lu Liao
NHNan-Sheng Huang
Nan-Sheng Huang
A chaotic secure communication scheme for a class of chaotic systems is presented. Based on the nonlinear state observer design technique, a systematic scheme is developed to achieve synchronization of chaotic systems and secure communication. The proposed scheme is then applied to a well-known Rossler chaotic system. Numerical simulation demonstrates the effectiveness of the proposed approach.