In silicon nanocrystal based metal–oxide–semiconductor memory structures, tuning of the electron tunneling distance between the Si substrate and Si nanocrystals located in the gate oxide is a crucial requirement for the pinpointing of optimal device architectures. In this work it is demonstrated that this tuning of the “injection distance” can be achieved by varying the ${\mathrm{Si}}^{+}$ ion energy or the oxide thickness during the fabrication of Si nanocrystals by ultralow-energy silicon implantation. Using an accurate cross-section transmission electron microscopy (XTEM) method, it is demonstrated that two-dimensional arrays of Si nanocrystals cannot be positioned closer than 5 nm to the channel by increasing the implantation energy. It is shown that injection distances down to much smaller values (2 nm) can be achieved only by decreasing the nominal thickness of the gate oxide. Depth profiles of excess silicon measured by time-of-flight secondary ion mass spectroscopy and Si nanocrystal locations determined by XTEM are compared with Monte-Carlo simulations of the implanted Si profiles taking into account dynamic target changes due to ion implantation, ion erosion, and ion beam mixing. This combination of experimental and theoretical studies gives a safe explanation regarding the unique technological route of obtaining Si nanocrystals at distances smaller than 5 nm from the channel: the formation of nanocrystals requires that the interface mixing due to collisional damage does not overlap with the range profile to the extent that there is no more a local maximum of Si excess buried in the ${\mathrm{SiO}}_2$ layer.

A sheet of spherical, well-separated, crystalline Ge nanodots embedded in ${\mathrm{SiO}}_2$ on top of a $\text{p-(001)}\mathrm{Si}$ wafer was fabricated by molecular beam epitaxy (MBE) combined with rapid thermal processing and characterized structurally and electrically. The average size of the Ge nanodots was estimated to be 4.5 nm with an average aerial density of ${\text{3×10}}^{11}\hspace{0.17em}{\mathrm{cm}}^{\text{−2}},$ situated at 4.4 nm in average away from the ${\mathrm{Si/SiO}}_2$ interface. Significant charge storage effects were observed through capacitance–voltage measurements of metal–oxide–semiconductor capacitors.

The effect of annealing in diluted oxygen versus inert environment on the structural and electrical characteristics of thin silicon dioxide layers with embedded Si nanocrystals fabricated by very low-energy silicon implantation (1 keV) is reported. Annealing in diluted oxygen increases the thickness of the control oxide, improves the integrity of the oxide and narrows the size distribution of the nanocrystals without affecting significantly their mean size $\text{(∼2\hspace{0.17em}}\mathrm{nm}\mathrm{).}$ Strong charge storage effects at low gate voltages and enhanced charge retention times are observed through electrical measurements of metal-oxide-semiconductor capacitors. These results indicate that a combination of low-energy silicon implants and annealing in diluted oxygen allows for the fabrication of improved low-voltage nonvolatile memory devices.

We study the implant-induced hydrogenated defects responsible for the Smart Cut™ layer transfer of Si (001) films. Different experimental methods are used to quantify the time dependence of the defect evolution and interactions during isothermal annealings. An optical characterization technique was developed for the statistical analysis of the formation and growth of micrometer size microcracks in the buried implanted layer. We show that the formation of molecular hydrogen is dominated by a transient phenomenon related to the rapid dissociation of the hydrogenated point defects. The impact of the ${\mathrm{H}}_2$ formation kinetics on the microcrack evolution is described and the physical mechanisms involved in their growth are identified. A comprehensive picture of the fracture phenomenon in H implanted Si leading to the full layer transfer is proposed and discussed.