In multitasking real-time systems it is required to compute the WCET of each task and also the effects of interferences between tasks in the worst case. This is complex with variable latency hardware usually found in the fetch path of commercial processors. Some methods disable cache replacement so that it is easier to model the cache behavior. Lock-MS is an ILP based method to obtain the best selection of memory lines to be locked in a dynamic locking instruction cache. In this paper we first propose a simple memory architecture implementing the next-line tagged prefetch, specially designed for hard real-time systems. Then, we extend Lock-MS to add support for hardware instruction prefetch. Our results show that the WCET of a system with prefetch and an instruction cache with size 5 % of the total code size is better than that of a system having no prefetch and cache size 80 % of the code. We also evaluate the effects of the prefetch penalty on the resulting WCET, showing that a system without prefetch penalties has a worst-case performance 95% of the ideal case. This highlights the importance of a good prefetch design. Finally, the computation time of our analysis method is relatively short, analyzing tasks of 96 KB with 106B paths in less than 3 minutes.

Time-Sensitive Networking (TSN) is an in-development technology that enables predictability over Ethernet or wireless networks. Network interfaces compliant with the IEEE 802.1Qbv standard provide different queues/gates on each bridge egress port. In this way, a global network schedule can be set by defining the opening and closing times (Gate Control List, GCL) for each gate. In this paper, we propose a new method to schedule GCLs by dividing the problem into several subproblems. We use Weighted Fair Queuing (WFQ) to set the ordering of frames, and then generate an Integer Linear Programming (ILP) model to optimize the TSN scenario. Next, we assign gates to the scheduled windows, trying to ensure frame isolation whenever possible. Our results show that we can schedule GCLs around 2 times faster than previous studies and up to 5.5 orders of magnitude faster if we choose to obtain any valid solution instead of the optimal one. In addition, we are able to schedule systems with utilization up to 85%, whereas previous papers reach 65%. Moreover, our approach does not need to predefine the number of windows or gates, as required by other methods.

The WCET computation is one of the main challenges in hard real-time systems, since all further analysis is based on this value. The complexity of this problem leads existing analysis methods to compute WCET bounds instead of the exact WCET. In this work we propose a technique to compute the exact instruction fetch contribution to the WCET (IFC-WCET) in presence of a LRU instruction cache. We prove that an exact computation does not need to analyze the full exponential number of possible execution paths, but only a bounded subset of them. In the benchmark codes we have studied, the IFC-WCET is up to 62% lower than a bound computed with a widely used approach, and the difference between the number of possible execution paths and the ones relevant for the analysis is extremely large.

accesses, provides both temporal and spatial reuse information, and does not require the exploration of explicit data access sequences. As a proof of concept we analyze the TACLeBench benchmark suite, showing that most loads/stores present data reuse, and how compiler optimizations affect it. Using a simple hit/miss estimation on our reuse results, the time devoted to data accesses in the worst case is reduced to 27% compared to an always-miss system, equivalent to a data hit ratio of 81%. With compiler optimization, such time is reduced to 6.5%.