Microwave imaging is an emerging breast cancer diagnostic technique, which aims at complementing already established methods like mammography, magnetic resonance imaging, and ultrasound. It offers two striking advantages: no-risk for the patient and potential low-cost for national health systems. So far, however, the prototypes developed for validation in labs and clinics used costly lab instruments such as a vector network analyzer (VNA). Moreover, the CPU time required by complex image reconstruction algorithms may not be compatible with the duration of a medical examination. In this paper, both these issues are tackled. Indeed, we present a prototype system based on low-cost and off-the-shelf microwave components, custom-made antennas, and a small form-factor processing system with an embedded field-programmable gate array for accelerating the execution of the imaging algorithm. We show that our low-cost system can compete with an expensive VNA in terms of accuracy, and it is more than 20x faster than a high-performance server at image reconstruction.

The International Technology Roadmap of semiconductors suggests that quantum-dot cellular automata (QCA) technology might be a possible CMOS substitute. In particular, magnetic quantum-dot cellular automata (MQCA) have recently drawn the attention of the researchers. Previous experimental works have demonstrated that MQCA are feasible, and can be fabricated with existing technological processes. They are also attractive due to their compactness and an extremely small power dissipation. Unlike in previous contributions, where architectural blocks are often presented without or only slightly considering their relations with technology, here we conceived, implemented, and described a complex MQCA computational block maintaining a clear link with technology. This link is achieved at different levels. At an architectural level, we propose the use of delay insensitive null convention logic (NCL) . It is implemented for MQCA in order to solve the “layout=timing” problem in the specific case of MQCA. We, thus, describe an architectural block at system level using a hardware description language (HDL). This NCL-HDL idea is adapted to a new structure, which we have called “snake clock,” proposed as a feasible solution for the problem of clock delivery, essential for MQCA operations. Furthermore, we demonstrated by means of accurate micromagnetic and finite element method simulations that the three-phase “snake-clock” NCL structure works correctly.

The quantum dot Cellular Automata (QCA) is an emerging nanotechnology that has gained significant research interest in recent years. Extremely small feature sizes, ultralow power consumption, and high clock frequency make QCA a potentially attractive solution for implementing computing architectures at the nanoscale. To be considered as a suitable CMOS substitute, the QCA technology must be able to implement complex real-time applications with affordable complexity. Low density parity check (LDPC) decoding is one of such applications. The core of LDPC decoding lies in the check node (CN) processing element which executes actual decoding algorithm and contributes toward overall performance and complexity of the LDPC decoder. This study presents a novel QCA architecture for partial parallel, layered LDPC check node. The CN executes Normalized Min Sum decoding algorithm and is flexible to support CN degree dc up to 20. The CN is constructed using a VHDL behavioral model of QCA elementary circuits which provides a hierarchical bottom up approach to evaluate the logical behavior, area, and power dissipation of the whole design. Performance evaluations are reported for the two main implementations of QCA i.e. molecular and magnetic.

In the post-CMOS scenario, field coupled nanotechnologies represent an innovative and interesting new direction for electronic nanocomputing. Among these technologies, nanomagnet logic (NML) makes it possible to finally embed logic and memory in the same device. To fully analyze the potential of NML circuits, design tools that mimic the CMOS design-flow should be used for circuit design. We present, in this paper, the latest and improved version of Torino Politecnico Nanotechnology (ToPoliNano), our design and simulation framework for field coupled nanotechnologies. ToPoliNano emulates the top-down design process of CMOS technology. Circuits are described with a VHSIC hardware description language netlist and layout is then automatically generated considering in-plane NML (iNML) technology. The resulting circuits can be simulated and performance can be analyzed. In this paper, we describe several enhancements to the tool itself, like a circuit editor for custom design of field coupled nanodevices, improved algorithms for netlist optimization and new algorithms for the place and route of iNML circuits. We have validated and analyzed the tool by using extensive metrics, both by using standard circuits and ISCAS'85 benchmarks. This contribution highlights the improvements of ToPoliNano, which is now a innovative and complete tool for the development of iNML technology.

In recent years, magnetic-based technologies, like nanomagnet logic (NML), are gaining increasing interest as possible substitutes of CMOS transistors. The possibility to mix logic and memory in the same device, coupled with a potential low power consumption, opens up completely new ways of developing circuits. The major issue of this technology is the necessity to use an external magnetic field as clock signal to drive the information through the circuit. The power losses due to the magnetic field generation potentially wipe out any advantages of NML. To solve this problem, new clock mechanisms were developed, based on spin transfer torque current and on voltage-controlled multiferroic structures that use magnetoelastic properties of magnetic materials, i.e., exploiting the possibility of influencing magnetization dynamics by means of the elastic tensor. In particular, the latter shows an extremely low power consumption. In this paper, we propose an innovative voltage-controlled magnetoelastic clock system aware of the technological constraints risen by modern fabrication processes. We show how circuits can be fabricated taking into account technological limitations, and we evaluate the performance of the proposed system. Results show that the proposed solution promises remarkable improvements over other NML approaches, even though state-of-the-art ideal multiferroic logic has in theory better performance. Moreover, since the proposed approach is technology-friendly, it gives a substantial contribution toward the fabrication of a full magnetic circuit and represents an optimal tradeoff between performance and feasibility.

Emerging computing technologies inherently exhibit high process and timing variation. Many researchers believe that an asynchronous approach is likely to play an enabling role in making these technologies feasible. This article compares the cost and performance of fully synchronous and mixed synchronous asynchronous implementations of quantum cellular automata, and makes the case that asynchrony is inevitable at the top levels of QCA designs.