The invention of batteries made it possible to store electricity for many purposes. One of the purposes is to keep the operations of WSN running without any interruptions. The main drawback of sensor nodes is their limited energy sources. The researcher introduces the energy harvesting (EH) concept for IoT-based WSNs to overcome energy limitations and charge the IoT devices. Many energy harvesting techniques have been introduced, such as solar, thermal, and flow-based ones, but radio frequency (RF)-based EH techniques received great attention from researchers due to their easy availability (from TV, radio, and wireless frequencies). In this paper, we have conducted a real-world experiment on Powercast energy harvesting devices and examined the behavior of sensed data in different scenarios, such as indoor, distance (feet/meters), and directional antennas. In our experiments, we have observed that when a device is removed from the charger, the energy scavenging process degrades and reaches a dead state. To stop a device from entering a dead state, we introduce a mobile charger technique to charge the device and find the optimal place for chargers and sensor devices. During mobile charging, we have also observed that when the directional antennas change their angle, the energy scavenging process degrades. To tackle these problems, we introduced two algorithms for directional and omni-directional antennas that efficiently solve the problem. Furthermore, we have obtained results for these scenarios and show that this technique has a promising output.

Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches.

Field Programmable Gate Arrays (FPGAs) based Ternary Content Addressable Memories (TCAMs) are widely used in high-speed networking applications.However, TCAMs are not present on state-of-the-art FPGAs and need to be emulated on SRAM-based memories (i.e., LUTRAMs and Block RAMs) which requires a large amount of FPGA resources. In this paper, we present an efficient methodology to implement FPGA-based TCAMs with significant resource savings compared to existing schemes. The proposed methodology exploits the fracturable nature of Look Up Tables (LUTs) and the built-in slice carry-chains for simultaneous mapping of two rules and its matching logic to a single FPGA slice. Multiple slices can be stacked together to build deeper and wider TCAMs in a modular way. The combination of all these techniques results in significant savings in resource utilization compared to existing approaches.

In the Identifier Locator Network Protocol (ILNP) networks, the existing mobility control schemes based on the centralized entity, called the Dynamic Domain Name Service (DDNS) server, such that all the control traffic is processed at the DDNS server. However, the centralized mobility schemes have significant limitations, such as control traffic overhead at the server and large handover delay. In order to resolve these issues, we propose a new mobility control scheme for ILNP networks, which manages the identifier-locators (ID-LOCs) in the fully distributed manner. In our scheme, each domain has a dedicated mobile DDNS (m-DDNS) server at the site border router (SBR). The m-DDNS server maintains two databases; i.e., home host register (HHR) and visiting host register (VHR), to support the roaming of mobile hosts. When a mobile host roams into a domain, the m-DDNS server in the visiting domain registers the host’s ID-LOC in the VHR and requests the update of HHR to the m-DDNS server in the home domain. Since the m-DDNS servers communicate each other directly, the ID-LOC mappings are managed without involvement of any central entities. We analyzed our proposed mobility scheme via numerical analysis and compared its performance with those of existing schemes. Numerical results showed that our scheme outperforms the existing mobility control schemes substantially in terms of control traffic overhead at the servers, total transmission delay and handover delay.

With the advent of digital computers, several prominent problems of digital circuit design emerged. A particular class of these problems, (called Type-2 problems) can be divided into two subclasses depending on whether an honest translator is possible or a sneaky translator is warranted. The case of an honest translator is simply an inverse problem of logic in which knowledge of the vectorial function Z(X) is utilised to produce its inverse vectorial function X(Z). Though an old method of solving type-2 problems was known almost half a century ago, two modern methods are now possible, namely the method of Boolean-equation solving and the method of input-domain constraining. The purpose of this paper is to expose and illustrate these two novel methods, with a stress on comparing them together and demonstrating their superiority to (as well as agreement with) the old conventional method. This purpose is achieved by way of three typical classical examples for which conventional solutions are somewhat tedious and cumbersome, while modern solutions are simple and insightful. Throughout these examples, the Karnaugh map is effectively utilised, either in its conventional version or in its variable-entered version. The Boolean-equation-solving method seems to involve certain unwarranted steps that might be possibly skipped. However, its utility can be extended beyond type-2 problems.