This paper proposes ZenFS+, a new storage backend of RocksDB for small-zone ZNS SSD. RocksDB has complicated internal operations such as flush and compaction. Flush and compaction run in separate threads, and it is well known that they closely interact around the sstables. Due to the concurrent storage I/O between flush and compaction, ZenFS presents unsatisfactory performance for small-zone ZNS SSD. We believe that ZenFS+ presents how ZNS SSD can support the performance and isolation of modern key-value stores. Leveraging the ZNS SSD, ZenFS+ intelligently identifies the independent zones group (IZG), which reveals the device’s internal parallelism. With the IZG information, ZenFS+ effectively isolates the flush workloads of RocksDB from compaction. Besides, ZenFS+ spreads the sstables to multiple IZGs so that the storage write can leverage the hardware parallelism. ZenFS+ presents up to 4.8x higher storage throughput for write-intensive microbenchmark and stabilizing 99.9P tail latency by 1/51 from existing ZenFS. Further, ZenFS+ implements proactive garbage collection, and presents sustainable performance over longer lifespan of the device.

The ZNS (Zoned NameSpace) interface shifts much of the storage maintenance responsibility to the host from the underlying SSDs (Solid-State Drives). In addition, it opens a new opportunity to exploit the internal parallelism of SSDs at both hardware and software levels. By orchestrating the mapping between zones and SSD-internal resources and by controlling zone allocation among threads, ZNS SSDs provide a distinct performance trade-off between parallelism and isolation. To understand and explore the design space of ZNS SSDs, we present ConfZNS (Configurable ZNS), an easy-to-configure and timing-accurate emulator based on QEMU. ConfZNS allows users to investigate a variety of ZNS SSD's internal architecture and how it performs with existing host software. We validate the accuracy of ConfZNS using real ZNS SSDs and explore performance characteristics of different ZNS SSD designs with real-world applications such as RocksDB, F2FS, and Docker environment.

NAND flash memory is the most widely used storage medium in embedded systems today due to its many advantages such as light weight, low power consumption, and shock resistance. Recently, solid state drives (SSDs), which use NAND flash memory to store data, are replacing conventional magnetic disks in laptops and some server computers. In the SSDs, to achieve both high performance and large capacity, a number of flash memory chips are connected to multiple buses and SSD firmware exploits parallel accesses by using interleaving and overlapping techniques. However, it is still unclear how many buses or chips should be used and how to drive those chips and buses to satisfy performance that may be required. To help answer these questions, we have developed a clock precision SSD simulator (CPS-SIM) that simulates the internal behavior of an SSD and that reports timing and utilization information. From the accurate timing and utilization results of CPS-SIM, we can discover the optimal hardware configuration including the number of buses and chips and their interconnections in an SSD. Also, it allows for fast development and verification of SSD firmware that runs an FTL (Flash Translation Layer) optimized for an SSD. Unlike FTLs for embedded flash memory, the FTL for an SSD must utilize the concurrency of the multiple chips and buses. By supporting concurrency, our CPS-SIM provides a flexible environment for design of SSD firmware that drives the multiple flash memory chips and also that schedules data transmissions via the multiple buses.

Employing multicore in mobile computing such as smartphone and IoT (Internet of Things) device is a double-edged sword. It provides ample computing capabilities required in recent intelligent mobile services including voice recognition, image processing, big data analysis, and deep learning. However, it requires a great deal of power consumption, which causes creating a thermal hot spot and putting pressure on the energy resource in a mobile device. In this paper, we propose a novel framework that integrates two well-known low-power techniques, DPM (Dynamic Power Management) and DVFS (Dynamic Voltage and Frequency Scaling) for energy efficiency in multicore mobile systems. The key feature of the proposed framework is adaptability. By monitoring the online resource usage such as CPU utilization and power consumption, the framework can orchestrate diverse DPM and DVFS policies according to workload characteristics. Real implementation based experiments using three mobile devices have shown that it can reduce the power consumption ranging from 22% to 79%, while affecting negligibly the performance of workloads.

This article traces the evolution of SSD (solid-state drive) interfaces, examining the transition from the block storage paradigm inherited from hard disk drives to SSD-specific standards customized to flash memory. Early SSDs conformed to the block abstraction for compatibility with the existing software storage stack, but studies and deployments show that this limits the performance potential for SSDs. As a result, new SSD-specific interface standards emerged to not only capitalize on the low latency and abundant internal parallelism of SSDs, but also include new command sets that diverge from the longstanding block abstraction. We first describe flash memory technology in the context of the block storage abstraction and the components within an SSD that provide the block storage illusion. We then describe the genealogy and relationships among academic research and industry standardization efforts for SSDs, along with some of their rise and fall in popularity. We classify these works into four evolving branches: (1) extending block abstraction with host-SSD hints/directives; (2) enhancing host-level control over SSDs; (3) offloading host-level management to SSDs; and (4) making SSDs byte-addressable. By dissecting these trajectories, the article also sheds light on the emerging challenges and opportunities, providing a roadmap for future research and development in SSD technologies.