This work presents a general, time-domain harmonic distortion estimation method, applicable to linear CMOS circuits characterized by weakly non-linear behavior, ranging from amplifiers and transconductors to filters, with any number of stages. It offers a compact, fast and systematic way to model circuits as a structure of interconnected Gm-stages, and estimates the harmonic distortion at every circuit node providing insight into the distortion contribution of every stage. The method uses a more involved model for each Gm-stage that also accounts for the dependence of its output current on cross-products of its input and output voltages, improving significantly the distortion estimation accuracy. The proposed method is easily implemented in MATLAB®, and intends to be integrated as a tool in EDA suites to speed-up distortion estimation. A number of examples are presented, illustrating the application of the method and validating its accuracy via comparison with Cadence® Spectre® simulation.

A 1.8V CMOS chopper four-quadrant analog multiplier, intending to serve as an autonomous IC block for low-frequency signal processing, is presented. Particular emphasis is laid upon achieving low output noise by means of chopper stabilization, while the multiplier's operation is based on the MOS Translinear Principle. The proposed design has been implemented and simulated in TSMC 0.18 μm CMOS process.

Detailed state-space modeling and analysis of a class of RF switched-capacitor power amplifiers achieving high efficiency, output power, and linearity are presented. Time-domain voltage and current waveforms are analytically obtained via the steady-state solution of the amplifier's model equations. The output power of the fundamental and that of the harmonics, as well as the drain efficiency of the switched-capacitor power amplifier (SCPA) are derived. The state-space model is implemented in MATLAB and all theoretical results are compared to Cadence Spectre simulation of the SCPA and are found to be in good agreement.

Open-circuit time-constant (OCTC) method is an approximate analytical method to estimate the 3 dB bandwidth of baseband circuits. Considerable saving in computational effort is achieved since a full analysis of the circuit is not required. The paper focuses on teaching and illustrating OCTC to senior undergraduate students. Two examples are presented to highlight the benefits gained by the approximate analysis technique and the perception of the students on the subject.

This work presents a power stage architecture that combines high–linearity with high–efficiency. The power stage is configured as a push–pull Class–A topology with two buck–converters providing its supply rails. The buck–converters continuously track the stage’s output with a small constant margin, creating a minimum, constant voltage drop on the output devices; thus, the stage’s efficiency is increased and its linearity is improved. Theoretical analysis of the topology and its feedback control are presented, while a design example is implemented and simulated in Cadence Spectre as proof–of–concept.