Space applications demand highly stable and reliable SRAM circuits for secure and the uninterrupted operation. In this paper, we propose advanced FinFET and self-refreshing logic-based 12T SRAM cell (WWL12T). The dual-k gate insulator and symmetric spacer are used to improve the reliability and performance of the FinFET. The outer side high-k insulator reduces the charge trapping to the gate oxide and improves the ON current along with reduced short channel effects. WWL12T uses extra word line for bit interleaving aware design and a feedback circuit for stable space applications. In the read operation, the extra P-type transistors are active according to the stored data bits and charge the storing nodes using bit-line voltages. The static noise margin and word line write margin of proposed WWL12T SRAM cell under worst case process variation and single charge trapping improve by 6.4% and 8.4%, respectively compared to existing 12T SRAM.

Negative bias temperature instability (NBTI) is a major reliability issue with the scaled devices at elevated temperature. The effect of NBTI increases with the time, and it increases the threshold voltage of PMOS. In this paper, an on-chip adaptive body bias (O-ABB) circuit to compensate the degradation due to NBTI aging is presented. The O-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin and word line write margin (WLWM). The O-ABB consists of standby leakage current (Iddq) sensor circuit, decision circuit and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre and post stress of 10 years NBTI aging. The proposed O-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM and WLWM decreases by 10.55%, 8.55%, and 3.25% respectively in the absence of O-ABB whereas hold SNM, read SNM and WLWM decreases by only 0.47%, 1.15% and 0.62% respectively, if O-ABB is used to compensate the degradation.

Negative bias temperature instability (NBTI) is a major time-dependent reliability concern with the pMOS transistor at elevated temperature. NBTI in pMOS is the severe dominating factor of circuit reliability as it increases the threshold voltage with time. In this paper, an nMOS-only Schmitt trigger with a voltage booster (NST-VB) circuit is proposed. The use of only an nMOS transistor in the critical path of the Schmitt trigger circuit drastically reduces the effect of NBTI on the circuit and, hence, improves performance. The proposed circuit is less affected by both inter-die and intra-die process variations in consequence of an nMOS-only structure. Because of NBTI, the increase in delay for the proposed NST-VB circuit is only 0.47% compared to 7.2% and 1.47% for the conventional Schmitt trigger and nMOS inverter, respectively, after the stress time of three years. The proposed NST-VB circuit is also validated with an s27 benchmark circuit from the ISCAS'89 benchmark set and found that it has a lower effect of NBTI compared to CMOS and Schmitt trigger inverter circuits. For the viability of the proposed circuit, figure-of-merit (FOM) is used as a performance metric and it is found that the proposed circuit has 15.11× improved FOM compared to the conventional Schmitt trigger circuit.

Environmental stress and advancing age is considered as the main cause of skin aging. However, environmental stress (especially UV radiations) accelerates the process of skin aging by manifolds. Coenzyme Q10 (CoQ₁₀), an essential compound of cellular bioenergetics also acts as a strong antioxidant and protects the body against aging. High molecular weight and structure specific lipophilic nature of this molecule is a bottle neck in effective delivery through topical route. Preparation of a novel proniosomal (PN) gel formulation of CoQ₁₀ employing systematic design of experiment (DoE) approach is a step ahead in transcending the constraints of the topical delivery. I-optimal mixture design was employed for systematic optimization of proniosomal formulation and evaluation of experimental data was performed for entrapment efficiency and in vitro release. Hydration of PN gel formulation with phosphate buffer (pH 7.5) results in submicron niosomes vesicles of spherical shape, which appeared dark against bright surroundings in TEM study. Animal skin was treated with UV radiations followed by treatment of PN gel CoQ₁₀ and conventional CoQ₁₀ present in a gel base. The effectiveness of the treatment was evaluated on the basis of biochemical estimation and histopathological studies. By using CoQ₁₀ PN gel formulation, levels of superoxide dismutase (SOD), catalase (CA), glutathione (GSH) and total proteins were restored by 81.3%, 72.1%, 74.8 and 77.1%, respectively to that of control group. Histopathological studies revealed better protection of skin treated with CoQ₁₀ PN gel compared to free CoQ₁₀. Prepared PN gel was found undisturbing with the normal histology hence, tolerated by animal skin compare to conventional gel.

In the implementation process of a convolution neural network (CNN)-based object detection system, the primary issues are power dissipation and limited throughput. Even though we utilize ultra-low power dissipation devices, the dynamic power dissipation issue will be difficult to resolve. During the operation of the CNN algorithm, there are several factors such as the heating problem generated from the massive computational complexity, the bottleneck generated in data transformation and by the limited bandwidth, and the power dissipation generated from redundant data access. This article proposes the low-power techniques, applies them to the CNN accelerator on the FPGA and ASIC design flow, and evaluates them on the Xilinx ZCU-102 FPGA SoC hardware platform and 45 nm technology for ASIC, respectively. Our proposed low-power techniques are applied at the register-transfer-level (RT-level), targeting FPGA and ASIC. In this article, we achieve up to a 53.21% power reduction in the ASIC implementation and saved 32.72% of the dynamic power dissipation in the FPGA implementation. This shows that our RTL low-power schemes have a powerful possibility of dynamic power reduction when applied to the FPGA design flow and ASIC design flow for the implementation of the CNN-based object detection system.

Power consumption and data processing speed of integrated circuits (ICs) is an increasing concern in many emerging Artificial Intelligence (AI) applications, such as autonomous vehicles and Internet of Things (IoT). Existing state-of-the-art SRAM architectures for AI computing are highly accurate and can provide high throughput. However, these SRAMs have problems that they consume high power and occupy a large area to accommodate complex AI models. A carbon nanotube field-effect transistors (CNFET) device has been reported as a potential candidates for AI devices requiring ultra-low power and high-throughput due to their satisfactory carrier mobility and symmetrical, good subthreshold electrical performance. Based on the CNFET and FinFET device’s electrical performance, we propose novel ultra-low power and high-throughput 8T SRAMs to circumvent the power and the throughput issues in Artificial Intelligent (AI) computation for autonomous vehicles. We propose two types of novel 8T SRAMs, P-Latch N-Access (PLNA) 8T SRAM structure and single-ended (SE) 8T SRAM structure, and compare the performance with existing state-of-the-art 8T SRAM architectures in terms of power consumption and speed. In the SRAM circuits of the FinFET and CNFET, higher tube and fin numbers lead to higher operating speed. However, the large number of tubes and fins can lead to larger area and more power consumption. Therefore, we optimize the area by reducing the number of tubes and fins without compromising the memory circuit speed and power. Most importantly, the decoupled reading and writing of our new SRAMs cell offers better low-power operation due to the stacking of device in the reading part, as well as achieving better readability and writability, while offering read Static Noise Margin (SNM) free because of isolated reading path, writing path, and greater pull up ratio. In addition, the proposed 8T SRAMs show even better performance in delay and power when we combine them with the collaborated voltage sense amplifier and independent read component. The proposed PLNA 8T SRAM can save 96%, while the proposed SE 8T SRAM saves around 99% in writing power consumption compared with the existing state-of-the-art 8T SRAM in FinFET model, as well as 99% for writing operation in CNFET model.