In this paper we report on the timing resolution obtained in a beam test with pions of 180 GeV/c momentum at CERN for the first production of 45 µm thick Ultra-Fast Silicon Detectors (UFSD). UFSD are based on the Low-Gain Avalanche Detector (LGAD) design, employing n-on-p silicon sensors with internal charge multiplication due to the presence of a thin, low-resistivity diffusion layer below the junction. The UFSD used in this test had a pad area of 1.7 mm 2 . The gain was measured to vary between 5 and 70 depending on the sensor bias voltage. The experimental setup included three UFSD and a fast trigger consisting of a quartz bar readout by a SiPM. The timing resolution was determined by doing Gaussian fits to the time-of-flight of the particles between one or more UFSD and the trigger counter. For a single UFSD the resolution was measured to be 34 ps for a bias voltage of 200 V, and 27 ps for a bias voltage of 230 V. For the combination of 3 UFSD the timing resolution was 20 ps for a bias voltage of 200 V, and 16 ps for a bias voltage of 230 V.In this paper we report on the timing resolution of the first production of 50 micro-meter thick Ultra-Fast Silicon Detectors (UFSD) as obtained in a beam test with pions of 180 GeV/c momentum. UFSD are based on the Low-Gain Avalanche Detectors (LGAD) design, employing n-on-p silicon sensors with internal charge multiplication due to the presence of a thin, low-resistivity diffusion layer below the junction. The UFSD used in this test belongs to the first production of thin (50 {\mu}m) sensors, with an pad area of 1.4 mm2. The gain was measured to vary between 5 and 70 depending on the bias voltage. The experimental setup included three UFSD and a fast trigger consisting of a quartz bar readout by a SiPM. The timing resolution, determined comparing the time of arrival of the particle in one or more UFSD and the trigger counter, for single UFSD was measured to be 35 ps for a bias voltage of 200 V, and 26 ps for a bias voltage of 240 V, and for the combination of 3 UFSD to be 20 ps for a bias voltage of 200 V, and 15 ps for a bias voltage of 240 V

Proceeding of the 10th International “Hiroshima” Symposium on the Development and Application of Semiconductor Tracking Detectors.-- et al.This paper reports the latest technological development on the Low Gain Avalanche Detector (LGAD) and introduces a new architecture of these detectors called inverse-LGAD (iLGAD). Both approaches are based on the standard Avalanche Photo Diodes (APD) concept, commonly used in optical and X-ray detection applications, including an internal multiplication of the charge generated by radiation. The multiplication is inherent to the basic n–p–p structure, where the doping profile of the p layer is optimized to achieve high field and high impact ionization at the junction. The LGAD structures are optimized for applications such as tracking or timing detectors for high energy physics experiments or medical applications where time resolution lower than 30 ps is required. Detailed TCAD device simulations together with the electrical and charge collection measurements are presented through this work.This work was developed in the framework of the CERN RD50 collaboration and financed by the Spanish Ministry of Economy and Competitiveness through the Particle Physics National Program (FPA2013-48308-C2-2-P, FPA2014-55295-C3-2-R and FPA2013-48387-C6-1-P). This project has received funding from the European Union's Horizon 2020 Research and Innovation program under Grant Agreement no. 654168 (AIDA-2020).Open Access funded by CERN.Peer Reviewe