The expansion of the concept of the Internet of Things (IoT), together with wireless sensor networks, has given rise to a wide range of IoT applications. This paper presents and describes the concept, theory of operation, and practical results of a Telecare-ECG (Electrocardiogram) Monitoring device, designed for the remote monitoring of out-of-hospital cardiac patients. ECG monitoring using the Telecare-ECG Monitor system ensures a better quality of life for patients and greater possibilities for the real-time monitoring and signaling of sporadic cardiac events, by recording instantaneous cardiac arrhythmias captured during certain activities or in the daily environment of the patient; furthermore, hospital resources are less impacted by this device than other devices. In accordance with the novelty and contribution of this paper to the field of ECG investigations, the results obtained in the analysis, testing, and validation of the Telecare-ECG Monitor system refer to the optimization of the functionality of the mobile ECG device under conditions that were as similar to reality as possible.

Today's electronic systems have evolved greatly and enable the design of systems that are safer, more competitive and also more flexible in terms of their built-in features and power consumption. As we see, the number of applications in the medical field and in adjacent areas have skyrocketed, so that monitoring terminals or mobile analysis systems can be purchased relatively easily. This paper presents and describes the concept, results and theory of operating the m-GreenCARDIO device, designed for remote monitoring of out-of-hospital patient's heart condition. This implementation helps to make medical instrumentation more efficient, making it accessible to a larger social range, by the means of Internet of Things (IoT). Thus, through this project, a real and flexible collection of ECG data from patients can be acquired, obtaining valuable information that can be used for remote research and diagnosis.

Multiple components affect the behavior of CPU execution tasks, mainly mutual exclusion during access to the shared resources and synchronous transmissions between tasks that require specific priorities. Referring to real-time task scheduling, the most important issues addressed are monitoring the deadline of the tasks, the probability of non-compliance with the deadline and ensuring that they are completed within the deadline imposed by the controlled system. This leads to the fact that a tasks set is feasible if the system has adequate resources to execute the tasks without losing any deadlines. To approach this challenge, this article addresses the feasibility analysis of runtime for real-time tasks to be performed in a virtual space before applying to a real embedded device. These processes take place offline, even before a system executes a set of tasks. In order to perform the feasibility analysis of the system, efforts are being made to provide virtual environments and simulators, such as the RISC-V ISA simulator and the WCET (Worst Case Execution Time) measurement, subsequently. These simulators have application-specific requirements, with their own advantages.

As RISC-V processors are increasingly considered for embedded real-time and control-oriented systems, evaluating how timing behavior changes under increasing task concurrency becomes essential. Adding runnable tasks can amplify preemptions, context-switch activity, response-time variability, execution jitter, and deadline pressure. Existing RISC-V simulation and virtual-platform environments mainly target architectural exploration, functional validation, or full-system execution, and do not directly provide a controlled workflow for isolating scheduler-induced timing degradation across large configuration spaces. This paper presents nSim-RV, a configurable and reproducible RISC-V simulation and orchestration framework for scheduler-aware timing scalability evaluation. The framework combines automated campaign generation, deterministic workload configuration, structured dataset aggregation, duplicate validation, and timing-oriented metric extraction. The evaluation compares a standard shared-pipeline execution model with an nMPRA-inspired preserved-context mode under identical scheduler and workload conditions. The campaign includes CoreMark, Dhrystone, and a deterministic synthetic RT-Control workload, 2–32 concurrent tasks, 50 k–1 M cycle observation windows, cache-disabled and cache-enabled configurations, and four-stage and five-stage pipeline organizations, resulting in 864 validated configurations. Results show that increasing task concurrency amplifies timing variability and deadline pressure. Preserved-context execution reduces switching-induced disturbance and delays or reduces higher-pressure timing behavior in several trajectories. Under the five-stage cache-disabled RT-Control configuration at N = 32, it reduces the deadline miss ratio from 3.74% to 2.21%, corresponding to a 41.1% relative reduction, with the clearest benefits observed for Dhrystone and RT-Control at intermediate–high task counts.

This paper presents a RISC-V pipeline simulation framework intended for the comparative evaluation of conventional pipelined execution and multi-context execution aligned with nMPRA (multi pipeline register architecture, where n is the degree of multiplication) and nHSE (hardware scheduler engine for n threads) real-time microarchitectural concepts. While instruction set architecture (ISA)-level simulators remain useful for functional validation, they provide limited visibility into pipeline behavior, context-switching penalties, and scheduler-driven execution effects. To address this limitation, the proposed framework combines an ISA reference mode with an explicit five-stage pipeline mode, enabling controlled comparison between functional execution and pipeline-level execution under the same workload conditions. The simulator supports scheduler-driven task activation and context switching, while enabling comparative evaluation of total cycles, retired instructions, pipeline stalls, context switches, and instructions per cycle (IPC). Representative experiments comparing ISA execution, standard pipelined execution, and an nMPRA-aligned configuration show that the framework can make switching-related timing effects directly observable. In particular, the results highlight the difference between a conventional shared pipeline and a context-preserving multi-context pipeline under the same task workload.